5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BIOS:1.03.E7 , EC:1.03.E5
RTCVCC
RTC_RST #
12.12ms (PSS t01)
G3 status
AC in status
15.52ms (PSS t08)
AC_PRESENT
102.ms
SUS_PWR_ACK
SLP_SUS# de-asser tion to SUS_CK stable:6.126m s (PSS t07)
SLP_SUS#
RSMRST3 to SUS_CK stable:102ms (PSS t07+t42)
SUS_CK
DD_ON
USB_CHARGE_EN
simultane ous
2.22ms
VDD5
3.3V
2.254ms
5V
3.152ms
PWR_ BT N#
121.94m s
34.6us (PSS t09)
SLP_S5#
SUSC#
17.19ms
DDR1.5 V_PWRG D
1.84ms
V_VDDQ_DIMM
1.439ms
65.7us (SUSC# to SUSB#) (PSS t10)
SUSB#
1.05V_LAN_ PWRG D
2.23ms
VDDQ_VT T
1.785ms
SLP_A#
same as SUSB#
1.05VM
1.38ms
1.613ms
3.3V S
3.24ms
1.5V S
3.77ms
5VS
8.95ms
ALL_SYS_PWRGD
controlled by DDR1.5V_PWRGD AND 1.05V_LAN_PWrGD
1.05VM to PM_MPWROK:7.43ms ( PSS t11)
6.25ms
+VCCIN (VCORE)
PM_PWR OK
SYS_PWROK
450ms
450ms
DMI
128.614us (PSS t39)
1.05VS
161.488us
1.05VM to1.05VS PSS t32
7.19866 ms
(1.05VS to PM_MPWROK) PSS t41
1.05VM
0ms (PM_MPW ROK to 1.05VM) PSS Tc
20.19us (PM_MPWR OK to 1.05VS) PSS Ti
13.4788us (SLP_A# to PM_MPWR OK) PSS Te
SLP_A#
0ms PSS Tk
7.23ms
1.05VM to PM_MPWROK PSS t11
S5 to S0
PWRON status
S0 to S3
SUSB#
PM_MPW ROK
1.05VS
20.6us (SUSB# to 1.05VS) PSS Tj
697.67us (SUSB# to VCC IN) PSS T f
SUS_STAT#
PLT_RST#
us PSS Tm
H_CPUPWRGD
41.73us PSS Tn
13.3268us (SUSB# to PM_MPW ROK) PSS Tw
CLOCK OUTPUT
32.0322us (H_CPUPWRGD to CLOCK) PSS Tr
54.5672us (CLOCK to SU SB#) PSS Ts
S3 to S0
+VCCIN (VCORE)
25.388ms PSS t13
H_CPUPWRGD
PM_MPW ROK
5.1407ms PSS t14
ALL_SYS_PWRGD
CLOCK OUTPUT
2.237ms
(CLOCK OUTPUT to H_CPUPW RGD)
24.946m s
(PM_MPWROK to H_CPUPWRGD) PSS t20
SYS_PWROK
s PSS t21
SUS_STAT#
s PSS t22
PLT_RST#
1.05VM
DMI
22.61us PSS t39
2.76ms PSS t19
S0 to S4
+VCCIN (VCORE)
SUSB#
PM_MPW ROK
1.05V S
33.8452us (SUSB# to 1.05VS) PSS Tj
70.067ms (SUSB# to VCC IN) PSS Tf
SUS_STAT#
PLT_RST#
us PSS Tm
H_CPUPWRGD
34.2816us PSS Tn
13.3438us (SUSB# to PM_MPW ROK) PSS Tw
CLOCK OUTPUT
31.9634us (H_CPUPWRGD to CLOCK) PSS Tr
55.3746us (CLOCK to SU SB#) PSS Ts
SUSC#
95.699us (SUSB# to SUSC #) PSS Tb
PM_DRAM_PWRG D
20.562us PSS Ti
VDD3
PM_BATLOW #
N15/170SD PWR SEQ
RSMRS T#
simultaneous
97.118ms (PSS t04, t05)
1.41ms
1.05V_LAN_ M
AC in status
1.05V S
PM_MPW ROK
6.29ms (PSS t14)
18.2 5us
DELAY_PWRGD
61.73ms (PSS t18)
PM_DRAM_PWRG D
H_CPUPWRGD
69.553ms (t20)
1.4765m s
PLT_RST#
Title
Size
Document Number Re v
Date: Sheet
of
1.0
[55] POWER SEQUENCE
Custom
55 55Tuesday, December 16, 2014
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size
Document Number Re v
Date: Sheet
of
1.0
[55] POWER SEQUENCE
Custom
55 55Tuesday, December 16, 2014
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size
Document Number Re v
Date: Sheet
of
1.0
[55] POWER SEQUENCE
Custom
55 55Tuesday, December 16, 2014
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/