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Intel BX80623I32100 User Manual
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Document Number: 324641
-008
2nd Generation Intel
®
Core™
Processor Family Desktop, Intel
®
Pentium
®
Processor Family Desktop,
and Intel
®
Celeron
®
Processor
Family Desktop
Datasheet, Volume 1
Supporting Intel
®
Core™ i7, i5, and i3 Desktop Processor Series
Supporting Intel
®
Pentium
®
Processor G800 and G600 Series
Supporting Intel
®
Celeron
®
Processor G500 and G400 Series
This is Volume 1 of 2
June 2013
2
Table of Contents
Default Chapter
3
Table of Contents
3
Revision History
8
1 Introduction
9
Desktop Platform System Block Diagram Example
10
Processor Feature Details
11
Supported Technologies
11
Interfaces
11
System Memory Support
11
PCI Express
12
PCI Express* Supported Configurations in Desktop Products
12
Direct Media Interface (DMI)
13
Platform Environment Control Interface (PECI)
14
Processor Graphics
14
Intel ® Flexible Display Interface (Intel ® FDI)
14
Power Management Support
15
Processor Core
15
System
15
Memory Controller
15
PCI Express
15
Direct Media Interface (DMI)
15
Processor Graphics Controller
15
Thermal Management Support
15
Package
16
Terminology
16
Related Documents
18
2 Interfaces
19
System Memory Interface
19
System Memory Technology Supported
19
Supported UDIMM Module Configurations
20
Supported SO-DIMM Module Configurations (AIO Only)
20
System Memory Timing Support
21
System Memory Organization Modes
21
Dual-Channel Mode - Intel ® Flex Memory Technology Mode
21
Single-Channel Mode
21
DDR3 System Memory Timing Support
21
Rules for Populating Memory Slots
22
Intel ® Flex Memory Technology Operation
22
Fma)
23
Just-In-Time Command Scheduling
23
Command Overlap
23
Out-Of-Order Scheduling
23
Memory Type Range Registers (Mtrrs) Enhancement
23
Data Scrambling
23
PCI Express* Interface
24
PCI Express* Architecture
24
PCI Express* Layering Diagram
24
Transaction Layer
25
Data Link Layer
25
Physical Layer
25
Packet Flow through the Layers
25
PCI Express* Configuration Mechanism
26
PCI Express* Port
26
PCI Express* Related Register Structures in the Processor
26
PCI Express* Lanes Connection
27
Direct Media Interface (DMI)
27
DMI Error Flow
27
Processor / PCH Compatibility Assumptions
27
PCI Express* Typical Operation 16 Lanes Mapping
27
DMI Link down
28
Processor Graphics Controller (GT)
28
Processor Graphics Controller Unit Block Diagram
28
And Video Engines for Graphics Processing
29
3D Engine Execution Units
29
Pipeline
29
Engine
30
Video Engine
30
Processor Graphics Display
31
Display Planes
31
Processor Display Block Diagram
31
Intel ® Flexible Display Interface
32
Intel Flexible Display Interface (Intel FDI)
32
Display Pipes
32
Display Ports
32
Multi-Graphics Controller Multi-Monitor Support
32
Platform Environment Control Interface (PECI)
33
Interface Clocking
33
Internal Clocking Requirements
33
Reference Clock
33
3 Technologies
35
Intel Virtualization Technology (Intel VT)
35
Intel IA-32, Intel
35
And Intel
35
VT-X) Objectives
35
VT-X) Features
36
VT) for
36
Intel I/O (Intel Virtualization Technology (Intel VT-D) Objectives
36
VT) for Directed
36
Intel I/O (Intel Virtualization Technology (Intel VT-D) Features
37
VT) for Directed
37
Intel Trusted Execution Technology (Intel TXT)
38
Intel VT-D) Features Not Supported..................................................37
38
HT Technology)
38
Hyper-Threading Technology
38
Intel Turbo Boost Technology
39
Intel
39
Intel Turbo Boost Technology Frequency
39
Intel Advanced Vector Extensions (Intel AVX)
40
Intel
40
Aes-Ni)
40
PCLMULQDQ Instruction
40
Intel ® 64 Architecture X2Apic
40
4 Power Management
43
Power States
43
Advanced Configuration and Power Interface (ACPI) States Supported
44
System States
44
Processor Core / Package Idle States
44
Integrated Memory Controller States
44
PCI Express* Link States
44
Processor Core / Package State Support
44
Direct Media Interface (DMI) States
45
Processor Graphics Controller States
45
Interface State Combinations
45
G, S, and C State Combinations
45
Processor Core Power Management
46
Enhanced Intel ® Speedstep ® Technology
46
Low-Power Idle States
46
Idle Power Management Breakdown of the Processor Cores
47
Thread and Core C-State Entry and Exit
47
Coordination of Thread Power States at the Core Level
47
Requesting Low-Power Idle States
48
Core C-States
48
Core C0 State
48
P_Lvlx to MWAIT Conversion
48
Core C1/C1E State
49
Core C3 State
49
Core C6 State
49
C-State Auto-Demotion
49
Package C-States
50
Coordination of Core Power States at the Package Level
50
Package C0
51
Package C1/C1E
51
Package C-State Entry and Exit
51
Package C3 State
52
Package C6 State
52
Integrated Memory Controller (IMC) Power Management
52
Disabling Unused System Memory Outputs
52
DRAM Power Management and Initialization
53
Conditional Self-Refresh
54
Initialization Role of CKE
54
DRAM I/O Power Management
55
Dynamic Power-Down Operation
55
PCI Express* Power Management
55
Direct Media Interface (DMI) Power Management
55
Graphics Power Management
56
Intel
56
Gpmt)
56
Graphics Performance Modulation Technology
56
Rapid Memory Power Management (Intel (also Known as Cxsr)
56
Rmpm)
56
Graphics Render C-State
56
Intel Smart 2D Display Technology (Intel S2DDT)
56
Thermal Power Management
57
Intel Graphics Dynamic Frequency
57
5 Thermal Management
59
6 Signal Description
61
Signal Description Buffer Types
61
System Memory Interface Signals
62
Memory Channel a Signals
62
Memory Reference and Compensation Signals
63
Memory Channel B Signals
63
Memory Reference and Compensation
63
Reset and Miscellaneous Signals
64
PCI Express*-Based Interface Signals
65
Intel ® Flexible Display Interface (Intel ® FDI) Signals
65
PCI Express* Graphics Interface Signals
65
Intel ® Flexible Display Interface (Intel ® FDI)
65
Direct Media Interface (DMI) Signals
66
Phase Lock Loop (PLL) Signals
66
Test Access Points (TAP) Signals
66
Direct Media Interface (DMI) Signals - Processor to PCH Serial Interface
66
Error and Thermal Protection Signals
67
Power Sequencing Signals
67
Processor Power Signals
68
Sense Signals
68
Ground and Non-Critical to Function (NCTF) Signals
68
Processor Internal Pull-Up / Pull-Down Resistors
69
7 Electrical Specifications
71
Power and Ground Lands
71
Decoupling Guidelines
71
Voltage Rail Decoupling
71
Processor Clocking (BCLK[0], BCLK#[0])
72
Phase Lock Loop (PLL) Power Supply
72
VCC Voltage Identification (VID)
72
VR 12.0 Voltage Identification Definition
73
System Agent (SA) VCC VID
76
Reserved or Unused Signals
76
VCCSA_VID Configuration
76
Signal Groups
77
Signal Groups 1
77
Test Access Port (TAP) Connection
78
Storage Conditions Specifications
79
Storage Condition Ratings
79
DC Specifications
80
Voltage and Current Specifications
80
Processor Core Active and Idle Mode DC Voltage and Current Specifications
80
Processor System Agent I/O Buffer Supply DC Voltage and Current Specifications
82
Supply DC Voltage and Current Specifications
83
Processor Graphics VID Based
83
Axg
83
DDR3 Signal Group DC Specifications
84
Control Sideband and TAP Signal Group DC Specifications
85
PCI Express* DC Specifications
85
Platform Environmental Control Interface (PECI) DC Specifications
86
PECI Bus Architecture
86
Example for PECI Host-Clients Connection
86
DC Characteristics
87
Input Device Hysteresis
87
PECI DC Electrical Limits
87
8 Processor Pin and Signal Information
89
Processor Pin Assignments
89
Socket Pinmap (Top View, Upper-Left Quadrant)
90
Socket Pinmap (Top View, Upper-Right Quadrant)
91
Socket Pinmap (Top View, Lower-Left Quadrant)
92
Socket Pinmap (Top View, Lower-Right Quadrant)
93
Processor Pin List by Pin Name
94
9 DDR Data Swizzling
109
DDR Data Swizzling Table - Channel a
110
DDR Data Swizzling Table - Channel B
111
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Intel BX80623I32100 Specifications
General
Brand
Intel
Model
BX80623I32100
Category
Computer Hardware
Language
English
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