JVC KD-A66 Service Manual

KD-A66A/B/C/E/J/U
No. 4193
The LC resonance peaking circuit mounted in parallel
with the emitter resistor of the recording amplifier
transistor boosts the high frequency of the recording
amplifier transistor. With a normal tape, the output
level of a 10 kHz signal is higher by about 9 dB than
that of a 1 kHz signal.
To avoid this problem, the selection of the capacitor in
the peaking circuit is performed to vary the compensa-
tion of high frequencies. In this case, the microcom-
puter emits a 3 binary bit signal, decodes it in 8 steps
and switches the appropriate analog switch in the
CMOS IC. Thus, the recording level is selected in the
range of +4 dB.
Fig. 9
Peak hold A/D converting circuit
In the KD-A66, a 12.5 KHz frequency is selected as the
equalizer tuning frequency to improve high band
frequency response. In a cassette tape deck with high
frequencies, the changes in levels such as are caused by
dropout, etc. are enlarged due to the base material of
the cassette tape and/or the wound state of the cassette
tape. If the optimim state is decided by the reproduc-
tion level such as in the B.E.S.T. system, this level
change causes incorrect setting of the respective values.
To avoid this problem in the KD-A66, a peak hold A/D
converter has been developed by the combination of a
peak hold circuit and a charge/discharge: circuit.
The peak hold A/D converting circuit permits stable
level detection even against high frequency dropout.
Block diagram is shown in Fig. 9 and timing chart in
Fig. 10.
The input signal is classified into a left or right channel
signal in IC801 by the Lch signal from the microcom-
puter, amplified by 1C802A and entered into the peak
hold circuit consisting of 1C802B, C802, D802 and
X805, which in turn detects the negative component of
the input signal accumulating at capacitor C802.
In the KD-A66, upon completion of the 40 msec oper-
ation of the peak hold circuit, $3 and S4 in 1C801 are
turned on by the ADC signal from the microcomputer.
Since $3 functions to apply +5V to the positive input
side of 1C802B, the output of 1C802B is clipped to
+5V and the loop in the peak hold circuit is opened by
diode D802.
At the same time S4 is turned on and capacitor C802 is
charged from the constant current source I1. Since a
constant current is supplied to this capacitor, the volt-
age in it linearly increases in the form of V=I1 x Time/c
+ Vo (initia! voltage).
Since capacitor C802 has been supplied with the
negative component of the input signal, when the volt-
age in it rises with the constant current charge, IC803A
detects the moment that this voltage exceeds OV, and
transmits that detection signal as an ADT signal to the
microcomputer.
The microcomputer measures the time from when the
40 msec peak hold operation is completed to when the
above voltage exceeds OV, to measure the signal level.
Fig. 10 is the timing chart. Here the input signal is sub-
ject to peak holding during the 40 msec period and
the constant current discharge is performed and the state
of OV excess is shown. AD1 is a normal signal, but this
indicates that stable measuring is possible should level
change (decrease) occur halfway as in AD2 and AD3.
WN A
ADC Teal fea AD3 ]
x805 —— :
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Marker signal detection
When recording while tuning the bias current, equaliza-
tion level and tape sensitivity, marker signals first enter
as shown in Figs 4 and 5. A 40 msec signal of 1 kHz
+50 dB is recorded two time as the marker signals with
a 40 msec blank between.
In the B.E.S.T. system, when the tape is rewound after
recording the test signals, it returns to its starting posi-
tion while counting the pulses from the tape counter.
This counting is not as accurate as when locating a 60
msec signal. For more accurate counting, the deck
waits for the said marker signals to appear in the repro-
duction state after rewinding the tape.
After the input signal is amplified by 1C802A in Fig. 9,
it is compared with -0.5V of IC803B in Fig. 5.
When this signal is entered, the output from IC803B is
inverted from +5V to -5V, thus transmitting the arrival
of the marker signals to the microcomputer.
After detecting the marker signals, the microcomputer
chekcs their pattern to discriminate the test signals,
thereby preventing faulty operation due to external
noise and ensuring accurate signal location.

JVC KD-A66 Specifications

General

Brand	JVC
Model	KD-A66
Category	Cassette Player
Language	English