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UM10462
LPC1
1U3x/2x/1x
User manual
Rev
. 5.5 — 21 Decembe
r 2016
User manual
Documen
t informat
ion
Info
Content
Keywords
LPC1
1U3x/2x/1x, ARM Co
rtex-M0, microcontroller,
LPC1
1U12,
LPC1
1U14, LPC1
1U13, USB, LPC1
1U22, LPC1
1U23, LPC1
1U24,
LPC1
1U34, LPC1
1U35, LPC1
1U36, LPC1
1U37,
LPC1
1U37H, I/O Hand
ler
Abstract
LPC1
1U3x/2x/1x User manual
2
Table of Contents
Chapter 1: Lpc11U3X/2X/1X Introductory Information
6
Introduction
6
Features
6
Chapter 25 : Supplementary Information
8
Ordering Information
8
Block Diagram
11
How to Read this Chapter
14
Memory Map
15
Chapter 2: Lpc11U3X/2X/1X Memory Mapping
16
Chapter 3: Lpc11U3X/2X/1X System Control Block
19
How to Read this Chapter
19
Introduction
19
Pin Description
19
Clocking and Power Control
19
Register Description
20
System Memory Remap Register
22
Peripheral Reset Control Register
23
System PLL Control Register
23
System PLL Status Register
24
USB PLL Control Register
24
USB PLL Status Register
25
System Oscillator Control Register
25
Watchdog Oscillator Control Register
26
Internal Resonant Crystal Control Register
27
System Reset Status Register
27
System PLL Clock Source Select Register
27
System PLL Clock Source Update Register
29
USB PLL Clock Source Select Register
29
USB PLL Clock Source Update Enable Register
29
Main Clock Source Select Register
30
Main Clock Source Update Enable Register
30
System Clock Divider Register
30
System Clock Control Register
31
SSP0 Clock Divider Register
33
USART Clock Divider Register
33
SSP1 Clock Divider Register
34
USB Clock Source Select Register
34
USB Clock Source Update Enable Register
34
USB Clock Divider Register
35
CLKOUT Clock Source Select Register
35
CLKOUT Clock Source Update Enable Register
35
CLKOUT Clock Divider Register
36
POR Captured PIO Status Register 0
36
POR Captured PIO Status Register 1
36
BOD Control Register
36
System Tick Counter Calibration Register
37
IRQ Latency Register
37
NMI Source Selection Register
38
Pin Interrupt Select Registers
38
USB Clock Control Register
39
USB Clock Status Register
39
Interrupt Wake-Up Enable Register 0
40
Interrupt Wake-Up Enable Register 1
40
Deep-Sleep Mode Configuration Register
41
Wake-Up Configuration Register
42
Power Configuration Register
43
Device ID Register
44
Flash Memory Access
45
Reset
45
Start-Up Behavior
46
Brown-Out Detection
46
Power Management
47
Reduced Power Modes and WWDT Lock Features
47
Active Mode
48
Power Configuration in Active Mode
48
Sleep Mode
48
Power Configuration in Sleep Mode
48
Programming Sleep Mode
48
Wake-Up from Sleep Mode
49
Deep-Sleep Mode
49
Power Configuration in Deep-Sleep Mode
49
Programming Deep-Sleep Mode
49
Wake-Up from Deep-Sleep Mode
50
Power-Down Mode
50
Power Configuration in Power-Down Mode
51
Programming Power-Down Mode
51
Wake-Up from Power-Down Mode
51
Deep Power-Down Mode
52
Mode
52
Programming Deep Power-Down Mode
52
Wake-Up from Deep Power-Down Mode
53
System PLL/USB PLL Functional Description
53
Lock Detector
54
Power-Down Control
54
Divider Ratio Programming
54
Post Divider
54
Feedback Divider
54
Changing the Divider Values
54
Frequency Selection
55
Normal Mode
55
Power-Down Mode
55
Chapter 4: Lpc11U3X/2X/1X Power Management Unit (PMU)
56
How to Read this Chapter
56
Introduction
56
Register Description
56
Power Control Register
56
General Purpose Registers 0 to 3
57
General Purpose Register 4
57
Functional Description
58
Chapter 5: Lpc11U3X/2X/1X Power Profiles
59
How to Read this Chapter
59
Features
59
Basic Configuration
59
General Description
59
Definitions
61
Clocking Routine
61
Set_Pll
61
Param0: System PLL Input Frequency and Param1: Expected System Clock
62
Param2: Mode
62
Param3: System PLL Lock Time-Out
62
Code Examples
63
Invalid Frequency
63
Exceeded)
63
Invalid Frequency Selection
63
Restrictions)
63
Exact Solution Cannot be Found (PLL)
63
Value
64
Expected Value
64
Power Routine
64
Set_Power
64
Param0: Main Clock
66
Param1: Mode
66
Param2: System Clock
66
Code Examples
66
Exceeded)
66
An Applicable Power Setup
66
Chapter 6: Lpc11U3X/2X/1X NVIC
68
How to Read this Chapter
68
Introduction
68
Features
68
Interrupt Sources
68
Register Description
70
Interrupt Set Enable Register 0 Register
71
Interrupt Clear Enable Register 0
72
Interrupt Set Pending Register 0 Register
73
Interrupt Clear Pending Register 0 Register
74
Interrupt Active Bit Register 0
75
Interrupt Priority Register 0
76
Interrupt Priority Register 1
77
Interrupt Priority Register 2
77
Interrupt Priority Register 3
77
Interrupt Priority Register 4
78
Interrupt Priority Register 5
78
Interrupt Priority Register 6
78
Interrupt Priority Register 7
79
How to Read this Chapter
80
Introduction
80
General Description
80
Chapter 7: Lpc11U3X/2X/1X I/O Configuration
81
Pin Function
81
Pin Mode
81
Hysteresis
82
Input Inverter
82
Input Glitch Filter
82
Open-Drain Mode
82
Analog Mode
82
C Mode
82
RESET Pin (Pin RESET_PIO0_0)
83
WAKEUP Pin (Pin PIO0_16)
83
Register Description
84
I/O Configuration Registers
86
RESET_PIO0_0 Register
86
PIO0_1 Register
87
PIO0_2 Register
88
PIO0_3 Register
88
PIO0_4 Register
89
PIO0_5 Register
89
PIO0_6 Register
90
PIO0_7 Register
91
PIO0_8 Register
91
PIO0_9 Register
92
SWCLK_PIO0_10 Register
93
TDI_PIO0_11 Register
94
TMS_PIO0_12 Register
95
PIO0_13 Register
96
TRST_PIO0_14 Register
97
SWDIO_PIO0_15 Register
98
PIO0_16 Register
99
PIO0_17 Register
100
PIO0_18 Register
100
PIO0_19 Register
101
PIO0_20 Register
102
PIO0_21 Register
103
PIO0_22 Register
103
PIO0_23 Register
104
PIO1_0 Register
105
PIO1_1 Register
106
PIO1_2 Register
107
PIO1_3 Register
107
PIO1_4 Register
108
PIO1_5 Register
109
PIO1_6 Register
109
PIO1_7 Register
110
PIO1_8 Register
111
PIO1_9 Register
112
PIO1_10 Register
112
PIO1_11 Register
113
PIO1_12 Register
114
PIO1_13 Register
114
PIO1_14 Register
115
PIO1_15 Register
116
PIO1_16 Register
117
PIO1_17 Register
117
PIO1_18 Register
118
PIO1_19 Register
119
PIO1_20 Register
120
PIO1_21 Register
120
PIO1_22 Register
121
PIO1_23 Register
122
PIO1_24 Register
123
PIO1_25 Register
123
PIO1_26 Register
124
PIO1_27 Register
125
PIO1_28 Register
125
PIO1_29 Register
126
PIO1_31 Register
127
Chapter 8: Lpc11U3X/2X/1X Pin Configuration
128
How to Read this Chapter
128
Pin Configuration
129
Lpc11U1X Pin Description
132
Lpc11U2X Pin Description
139
Lpc11U3X Pin Description
145
Chapter 9: Lpc11U3X/2X/1X GPIO
153
How to Read this Chapter
153
Basic Configuration
153
Features
153
GPIO Pin Interrupt Features
153
GPIO Group Interrupt Features
153
GPIO Port Features
154
Introduction
154
GPIO Pin Interrupts
154
GPIO Group Interrupt
154
GPIO Port
154
Register Description
154
GPIO Pin Interrupts Register Description
157
Pin Interrupt Mode Register
157
Pin Interrupt Level (Rising Edge) Interrupt Enable Register
157
Pin Interrupt Level (Rising Edge) Interrupt Set Register
157
Pin Interrupt Level (Rising Edge Interrupt) Clear Register
158
Pin Interrupt Active Level (Falling Edge) Interrupt Enable Register
158
Pin Interrupt Active Level (Falling Edge) Interrupt Set Register
159
Pin Interrupt Active Level (Falling Edge Interrupt) Clear Register
159
Pin Interrupt Rising Edge Register
160
Pin Interrupt Falling Edge Register
160
Pin Interrupt Status Register
161
GPIO GROUP0/GROUP1 Interrupt Register Description
161
Grouped Interrupt Control Register
161
GPIO Grouped Interrupt Port Polarity Registers
161
GPIO Grouped Interrupt Port Enable Registers
162
GPIO Port Register Description
163
GPIO Port Byte Pin Registers
163
GPIO Port Word Pin Registers
163
GPIO Port Direction Registers
164
GPIO Port Mask Registers
164
GPIO Port Pin Registers
165
GPIO Masked Port Pin Registers
165
GPIO Port Set Registers
166
GPIO Port Clear Registers
166
GPIO Port Toggle Registers
166
Functional Description
167
Reading Pin State
167
GPIO Output
167
Masked I/O
168
GPIO Interrupts
168
Pin Interrupts
168
Group Interrupts
169
Recommended Practices
169
Chapter 10 : Lpc11U3X/2X/1X USB On-Chip Drivers
170
How to Read this Chapter
170
Introduction
170
USB Driver Functions
170
Calling the USB Device Driver
171
NXP B.V. 2016. All Rights Reserved
172
Usb Api
172
Bm_T
172
Descriptor
173
Cdc_Header_Descriptor
173
Cdc_Line_Coding
173
Cdc_Union_1Slave_Descriptor
174
Cdc_Union_Descriptor
174
Dfu_Status
174
Hid_Descriptor
174
Hid_Report_T
175
Msc_Cbw
176
Msc_Csw
176
Request_Type
176
Usb_Common_Descriptor
176
Usb_Core_Descs_T
177
Usb_Device_Qualifier_Descriptor 177 _Usb_Dfu_Func_Descriptor
177
Usb_Interface_Descriptor
178
Usb_Other_Speed_Configuration 178 _Usb_Setup_Packet
179
Usb_String_Descriptor
179
Wb_T
180
Usbd_Api
180
Usbd_Api_Init_Param
181
Usbd_Cdc_Api
184
Usbd_Cdc_Init_Param
185
Usbd_Core_Api
194
Usbd_Dfu_Api
197
Usbd_Dfu_Init_Param
198
Usbd_Hid_Api
200
Usbd_Hid_Init_Param
201
Usbd_Hw_Api
207
Usbd_Msc_Api
215
Usbd_Msc_Init_Param
216
Chapter 11: Lpc11U3X/2X/1X USB2.0 Device Controller
221
How to Read this Chapter
221
Basic Configuration
221
Features
221
General Description
221
USB Software Interface
223
Fixed Endpoint Configuration
223
Softconnect
223
Interrupts
224
Suspend and Resume
224
Frame Toggle Output
224
Clocking
225
Pin Description
225
Register Description
225
USB Device Command/Status Register
225
USB EP Command/Status List Start Address
225
USB Data Buffer Start Address
225
USB Link Power Management Register
225
Epbufcfg
225
(Devcmdstat)
226
Intsetstat
226
USB Info Register (INFO)
228
(Epliststart)
228
(Databufstart)
229
(Lpm)
229
USB Endpoint Skip (EPSKIP)
230
USB Endpoint Buffer in Use (EPINUSE)
230
USB Interrupt Status Register (INTSTAT)
231
USB Interrupt Enable Register (INTEN)
232
USB Set Interrupt Status Register
233
USB Interrupt Routing Register
233
(Introuting)
233
USB Endpoint Toggle (EPTOGGLE)
233
Functional Description
234
Endpoint Command/Status List
234
Control Endpoint 0
237
Generic Endpoint: Single-Buffering
238
Generic Endpoint: Double-Buffering
239
Special Cases
239
Use of the Active Bit
239
Generation of a STALL Handshake
239
Clear Feature (Endpoint Halt)
239
Set Configuration
240
USB Wake-Up
240
Waking up from Deep-Sleep and Power-Down Modes on USB Activity
240
Remote Wake-Up
240
Chapter 12 : Lpc11U3X/2X/1X USART
242
How to Read this Chapter
242
Basic Configuration
242
Features
242
Pin Description
242
Register Description
243
USART Receiver Buffer Register (When DLAB = 0, Read Only)
244
USART Transmitter Holding Register
244
DLAB = 0, Write Only)
244
USART Divisor Latch LSB and MSB Registers
245
(When DLAB = 1)
245
USART Interrupt Enable Register
245
Dlab = 0)
245
USART Interrupt Identification Register
246
Only)
248
USART FIFO Control Register (Write Only)
248
USART Line Control Register
249
USART Modem Control Register
250
Auto-Flow Control
251
Auto-RTS
251
Auto-CTS
252
USART Line Status Register (Read-Only)
253
USART Modem Status Register
255
USART Scratch Pad Register
255
USART Auto-Baud Control Register
256
Auto-Baud
256
Auto-Baud Modes
257
Irda Control Register
258
USART Fractional Divider Register
260
Baud Rate Calculation
261
Example 1: UART_PCLK = 14.7456 Mhz, BR
263
Example 2: UART_PCLK = 12.0 Mhz, BR = 115200
263
USART Oversampling Register
263
USART Transmit Enable Register
264
UART Half-Duplex Enable Register
265
Smart Card Interface Control Register
265
USART RS485 Control Register
266
USART RS-485 Address Match Register
267
USART RS-485 Delay Value Register
267
USART Synchronous Mode Control Register 268 Functional Description
270
RS-485/EIA-485 Modes of Operation
270
RS-485/EIA-485 Normal Multidrop Mode
270
Mode
270
RS-485/EIA-485 Auto Direction Control
271
RS485/EIA-485 Driver Delay Time
271
RS485/EIA-485 Output Inversion
271
Smart Card Mode
271
Smart Card Set-Up Procedure
272
Architecture
273
Chapter 13: Lpc11U3X/2X/1X SSP/SPI
275
How to Read this Chapter
275
Basic Configuration
275
Features
275
General Description
275
Pin Description
276
Register Description
276
SSP/SPI Control Register 0
277
SSP/SPI Control Register 1
278
SSP/SPI Data Register
279
SSP/SPI Status Register
280
SSP/SPI Clock Prescale Register
280
SSP/SPI Interrupt Mask Set/Clear Register
280
SSP/SPI Raw Interrupt Status Register
281
SSP/SPI Masked Interrupt Status Register
281
SSP/SPI Interrupt Clear Register
282
Functional Description
282
Texas Instruments Synchronous Serial Frame Format
282
SPI Frame Format
283
Control
283
SPI Format with CPOL=0,CPHA=0
284
SPI Format with CPOL=0,CPHA=1
285
SPI Format with CPOL = 1,CPHA = 0
285
SPI Format with CPOL = 1,CPHA = 1
287
Semiconductor Microwire Frame Format
287
Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode
289
Chapter 14: Lpc11U3X/2X/1X I2C-Bus Controller
290
How to Read this Chapter
290
Basic Configuration
290
Features
290
Applications
290
General Description
290
I 2 C Fast-Mode Plus
291
Pin Description
292
Register Description
292
I 2 C Control Set Register (CONSET)
293
I 2 C Status Register (STAT)
295
I 2 C Data Register (DAT)
295
I 2 C Slave Address Register 0 (ADR0)
296
C SCL HIGH and LOW Duty Cycle Registers (SCLH and SCLL)
296
Cycle
296
I 2 C Control Clear Register (CONCLR)
297
I 2 C Monitor Mode Control Register (MMCTRL) 297 Interrupt in Monitor Mode
298
Loss of Arbitration in Monitor Mode
299
I 2 C Slave Address Registers (ADR[1, 2, 3]) . 299 I 2 C Data Buffer Register (DATA_BUFFER)
299
I 2 C Mask Registers (MASK[0, 1, 2, 3])
300
Functional Description
300
Input Filters and Output Stages
301
Address Registers, ADR0 to ADR3
302
Address Mask Registers, MASK0 to MASK3
302
Comparator
302
Shift Register, DAT
302
Arbitration and Synchronization Logic
302
Serial Clock Generator
303
Timing and Control
304
Control Register, CONSET and CONCLR
304
Status Decoder and Status Register
304
C Operating Modes
304
Master Transmitter Mode
304
Master Receiver Mode
305
Slave Receiver Mode
306
Slave Transmitter Mode
307
Details of I C Operating Modes
307
Master Transmitter Mode
308
Master Receiver Mode
312
Slave Receiver Mode
315
Slave Transmitter Mode
319
Miscellaneous States
321
STAT = 0Xf8
321
STAT = 0X00
321
Some Special Cases
322
Simultaneous Repeated START Conditions from
322
Two Masters
322
Data Transfer after Loss of Arbitration
323
Forced Access to the I
323
Bus
323
C-Bus Obstructed by a LOW Level on SCL or SDA
324
Bus Error
324
C State Service Routines
324
Initialization
325
C Interrupt Service
325
The State Service Routines
325
Adapting State Services to an Application
325
Software Example
325
Initialization Routine
325
Start Master Transmit Function
325
Start Master Receive Function
326
I 2 C Interrupt Routine
326
Non Mode Specific States
326
State: 0X00
326
Master States
326
State: 0X08
326
State: 0X10
327
Master Transmitter States
327
State: 0X18
327
State: 0X20
327
State: 0X28
327
State: 0X30
328
State: 0X38
328
Master Receive States
328
State: 0X40
328
State: 0X48
328
State: 0X50
328
State: 0X58
329
Slave Receiver States
329
State: 0X60
329
State: 0X68
329
State: 0X70
329
State: 0X78
330
State: 0X80
330
State: 0X88
330
State: 0X90
330
State: 0X98
331
State: 0Xa0
331
Slave Transmitter States
331
State: 0Xa8
331
State: 0Xb0
331
State: 0Xb8
331
State: 0Xc0
332
State: 0Xc8
332
Chapter 15: Lpc11U3X/2X/1X 16-Bit Counter/Timers CT16B0/1
333
How to Read this Chapter
333
Basic Configuration
333
Features
333
Applications
334
General Description
334
Pin Description
334
Register Description
334
Interrupt Register
337
Timer Control Register
337
Timer Counter
338
Prescale Register
338
Prescale Counter Register
338
Match Control Register
339
Match Registers
340
Capture Control Register
340
Capture Registers
342
External Match Register
343
Count Control Register
344
PWM Control Register
347
Rules for Single Edge Controlled PWM Outputs
348
Example Timer Operation
349
Architecture
349
Chapter 16 : Lpc11U3X/2X/1X 32-Bit Counter/Timers CT32B0/1
351
How to Read this Chapter
351
Basic Configuration
351
Features
351
Applications
352
General Description
352
Pin Description
352
Register Description
352
Interrupt Register
355
Timer Control Register
355
Timer Counter Registers
356
Prescale Register
356
Prescale Counter Register
356
Match Control Register
357
Match Registers
358
Capture Control Register
358
Capture Registers
360
External Match Register
360
Count Control Register
362
PWM Control Register
364
Rules for Single Edge Controlled PWM Outputs
365
Example Timer Operation
366
Architecture
367
Chapter 17: Lpc11U3X/2X/1X Windowed Watchdog Timer (WWDT)
369
How to Read this Chapter
369
Basic Configuration
369
Features
369
Applications
370
Description
370
Block Diagram
370
Clocking and Power Control
371
Using the WWDT Lock Features
372
Accidental Overwrite of the WWDT Clock
372
Changing the WWDT Clock Source
372
Changing the WWDT Reload Value
372
Register Description
373
Watchdog Mode Register
373
Watchdog Timer Constant Register
375
Watchdog Feed Register
375
Watchdog Timer Value Register
376
Watchdog Clock Select Register
376
Watchdog Timer Warning Interrupt Register . 376 Watchdog Timer Window Register
377
Watchdog Timing Examples
377
Chapter 18: Lpc11U3X/2X/1X System Tick Timer
379
How to Read this Chapter
379
Basic Configuration
379
Features
379
General Description
379
Register Description
380
System Timer Control and Status Register
380
System Timer Reload Value Register
381
System Timer Current Value Register
381
System Timer Calibration Value Register
382
Functional Description
382
Example Timer Calculations
382
Example (System Clock = 50 Mhz)
382
Chapter 19: Lpc11U3X/2X/1X ADC
383
How to Read this Chapter
383
Basic Configuration
383
Features
383
Pin Description
383
Register Description
384
A/D Control Register (CR - 0X4001 C000)
385
A/D Global Data Register (GDR - 0X4001 C004)
386
A/D Interrupt Enable Register (INTEN - 0X4001 C00C)
387
A/D Data Registers (DR0 to DR7 - 0X4001 C010 to 0X4001 C02C)
387
A/D Status Register (STAT - 0X4001 C030) . 387 Operation
388
Hardware-Triggered Conversion
388
Interrupts
388
Accuracy Vs. Digital Receiver
388
How to Read this Chapter
389
Chapter 20: Lpc11U3X/2X/1X Flash Programming Firmware
390
Bootloader
390
Features
390
Description
390
Memory Map after any Reset
391
Flash Content Protection Mechanism
391
Criterion for Valid User Code
392
ISP/IAP Communication Protocol
393
ISP Command Format
393
ISP Response Format
393
ISP Data Format
393
ISP Flow Control
393
ISP Command Abort
393
Interrupts During ISP
393
Interrupts During IAP
394
RAM Used by ISP Command Handler
394
RAM Used by IAP Command Handler
394
USB Communication Protocol
394
Usage Note
395
Boot Process Flowchart
396
Sector Numbers
397
Lpc11U1X/2X
397
Lpc11U3X
397
Code Read Protection (CRP)
398
ISP Entry Protection
400
ISP Commands
401
Unlock <Unlock Code
401
Set Baud Rate <Baud Rate> <Stop Bit
402
4
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NXP Semiconductors LPC11U3x Specifications
General
Brand
NXP Semiconductors
Model
LPC11U3x
Category
Microcontrollers
Language
English
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