Data from the processor data bus is written into data
latch U541 when the MODECON (mode control) bit from
U550 returns HI (after the PWRUP reset goes HI). These
Mode Control Register
Mode Control Register U541 and associated gating cir-
cuits composed of U340, U442, U423B, and U350C, con-
trol the operating modes of the various display state
machines.
Once enabled, the three lowest address bits are used
to select one of the eight outputs from U550. These out-
puts, when LO, enable or load one of the eight display
registers. Enabling of these individual registers is explained
in more detail in the specific register descriptions.
The enable inputs for U550 are controlled by the Sys-
tem j!P. The DISPSEL (display select) is an address-
decoded signal produced on the Processor board when
any of the display memory addresses are output by the
System j!P. Negative OR gate U450D provides an enable
to U550 whenever the System j!P is trying to read or
write. Address bit A3 provides the final enable when it
is HI.
Register Select
The Register Select stage, composed of U550 and
U450D (along with the System j!P address decoding),
address decodes the three LSBs of the System j!P
address bus to enable any of eight display "registers" for
a read or write. These registers control such things as
display mode (hOWthe stored data is displayed, either XY
or YT), which waveforms are displayed, and whether or
not cursors and readout are to be displayed.
Each of these display types is controlled and initiated
by the System j!P. The acquired waveform data points are
written into the Display RAMs by the Waveform j!P and
the readout data is written in by the System j!P. Display of
this stored data is controlled by the System j!P through
data latched into the several display registers. The data
written to the registers determines what type of display
should be produced, how long (number of data points) it
should be, and when it should start.
memory space (stored in the Horizontal RAM). To display
the readout, the Readout State Machine sequentially
reads through the readout memory and displays the
required character at the corresponding (memory-mapped)
location on the crt screen. Each displayed character con-
sists of a sequence of individual dots produced by the
Readout State Machine.
3-64
For readout displays, the face of the crt is vertically
divided into 16 character lines each having 40 horizontal
character positions on the line. Each of these character
positions corresponds to a specific location in the readout
For YT waveform displays, the Display State Machine
generates 512 linearly spaced points across the face of
the crt (horizontally). Each of these points may be
displayed at any of 256 vertical positions on the crt. For
XY displays, each of the 512 points that make up a
waveform may be placed anywhere on the screen in a 256
X 256 matrix.
The Display Control System (diagram 17) produces the
crt waveform and readout displays from data stored in the
Display RAM. The data, originally stored by the Waveform
j!P or the System j!P, is read out of the RAM and is used
to produce the individual dots that make up both
waveform and readout displays. The Display System has
two "state machines" for converting the stored data into
the horizontal and vertical deflections that produce the
waveform dots and readout characters.
DISPLAY CONTROL
Diagnostic Buffers
The Diagnostic Buffers, U141 (vertical) and U243 (hor-
izontal), allow the System j!P to monitor the data being
applied to the Vertical DAC and Horizontal DAC
respectively. By forcing known data patterns through the
various data paths and observing the data arriving at the
DAC inputs, the diagnostic routines can verify functionality
of much of the display system hardware. The buffers are
enabled during diagnostics via the address-decoded Regis-
ter Select logic.
Horizontal DAC
Operation of Horizontal DAC U250 is identical to that of
the Vertical DAC and produces the horizontal-deflection
signal currents that drive the Horizontal Output Amplifier.
Vertical DAC U142 generates complementary vertical-
deflection currents used to drive the vertical deflection sys-
tem from the digital data applied to its inputs. The data
that appears at the DAC inputs is selected by the
microprocessor via the Mode-Control Register and deter-
mines what type of display will be generated. The
exclusive-OR gate U350A inverts bit DY9 during "non-
readout" displays to create "bipolar" data relative to the
vertical (graticule) center of the crt.
Vertical DAC
Theory of Operation-2430 Service
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