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Texas Instruments TMS320 DSP User Manual
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TMS320
DSP
Algorithm
Standard
Rules
and
Guidelines
User's
Guide
Literature
Number:
SPRU352G
June
2005
–
Revised
February
2007
2
Table of Contents
Default Chapter
3
Table of Contents
3
Preface
7
1 Overview
9
Scope of the Standard
10
TMS320 DSP Algorithm Standard Elements
10
Rules and Guidelines
11
Requirements of the Standard
11
Goals of the Standard
12
Intentional Omissions
12
System Architecture
13
Frameworks
13
DSP Software Architecture
13
Algorithms
14
Core Run-Time Support
14
2 General Programming Guidelines
15
Use of C Language
16
Threads and Reentrancy
16
Threads
16
Preemptive Vs. Non-Preemptive Multitasking
17
Reentrancy
17
Example
18
Data Memory
19
Memory Spaces
20
Scratch Versus Persistent
20
Scratch Vs Persistent Memory Allocation
21
Algorithm Versus Application
22
Data Memory Types
22
Program Memory
23
ROM-Ability
23
Use of Peripherals
24
3 Algorithm Component Model
25
Interfaces and Modules
26
Module Interface and Implementation
26
External Identifiers
27
Naming Conventions
28
Module Initialization and Finalization
28
Module Instance Objects
28
Design-Time Object Creation
29
Run-Time Object Creation and Deletion
29
Module Object Creation
29
Example Module Object
29
Module Configuration
30
Example Module
30
Multiple Interface Support
31
Interface Inheritance
32
Summary
32
Algorithms
33
Example Implementation of IALG Interface
33
Packaging
34
Object Code
34
Debug Verses Release
35
Header Files
35
4 Algorithm Performance Characterization
37
Data Memory
38
Heap Memory
38
Stack Memory
39
Static Local and Global Data Memory
39
Program Memory
40
Interrupt Latency
41
Execution Time
41
MIPS Is Not Enough
41
Execution Time Model
42
Execution Timeline for Two Periodic Tasks
42
5 DSP-Specific Guidelines
45
CPU Register Types
46
Register Types
46
Use of Floating Point
47
Tms320C6Xxx Rules and Guidelines
47
Data Models
47
Endian Byte Ordering
47
Program Model
47
Register Conventions
48
Status Register
48
Interrupt Latency
49
Tms320C54Xx Rules and Guidelines
49
Data Models
49
Program Models
49
Register Conventions
51
Status Registers
51
Interrupt Latency
52
Tms320C55X Rules and Guidelines
52
Data Models
52
Stack Architecture
52
Program Models
53
Relocatability
53
Register Conventions
54
Status Bits
55
Tms320C24Xx Guidelines
57
Data Models
57
General
57
Program Models
57
Register Conventions
57
Interrupt Latency
58
Status Registers
58
Tms320C28X Rules and Guidelines
58
Data Models
58
Program Models
59
Register Conventions
59
Status Registers
59
Interrupt Latency
60
6 Use of the DMA Resource
61
Overview
62
Algorithm and Framework
62
Requirements for the Use of the DMA Resource
63
Logical Channel
63
Data Transfer Properties
64
Data Transfer Synchronization
64
Transfer Properties for a 1-D Frame
64
Frame Index and 2-D Transfer of N-1 Frames
64
Abstract Interface
65
Resource Characterization
66
Runtime Apis
67
Strong Ordering of DMA Transfer Requests
67
Submitting DMA Transfer Requests
68
Device Independent DMA Optimization Guideline
68
C6Xxx Specific DMA Rules and Guidelines
69
Cache Coherency Issues for Algorithm Producers
69
C55X Specific DMA Rules and Guidelines
70
Supporting Packed/Burst Mode DMA Transfers
70
Addressing Automatic Endianism Conversion Issues
71
Minimizing Logical Channel Reconfiguration Overhead
71
Inter-Algorithm Synchronization
71
Non-Preemptive System
71
Preemptive System
72
Rules and Guidelines
75
A.1 General Rules
76
General Rules
76
A.3 DMA Rules
77
DMA Rules
77
Performance Characterization Rules
77
A.4 General Guidelines
78
General Guidelines
78
A.5 DMA Guidelines
79
DMA Guidelines
79
Core Run-Time Apis
81
DSP/BIOS Run-Time Support Library
82
TI C-Language Run-Time Support Library
82
C Bibliography
83
Books
83
Urls
83
C.1 Books
83
C.2 Urls
83
D Glossary
85
Glossary of Terms
85
D.1 Glossary of Terms
85
4
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Texas Instruments TMS320 DSP Specifications
General
Brand
Texas Instruments
Model
TMS320 DSP
Category
Computer Hardware
Language
English
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