Alto Hardware Manual
Conditions
if
IR[O]
= 1
elseif IR[l-
2]
:;t:.
3
elseif
IR[3-7]
= 0
elseif
IR[3-7]
= 1
elseif
IR[3-7]
= 2
elseif
IR[3-7]
= 3
elseif
IR[3-7]
= 4
elseif
IR[3-7]
=
llB
elseif
IR[3-7]
=
12B
elseif IR[3-7]::;:
16B
elseif
IR[3-7]
=
37B
else
ORed
onto
NEXT
then
3-IR[8-9]
then
IR[S]
then 2
then 5
then 3
then 6
then 7
then 4
then 4
then 1
. then
17B
16B
Section 3: Emulator
Comment
the complement
of
the
SH
field
of
IR
the Indirect bit
of
IR
CYCLE
RAMTRAP
NOPAR
-- parameterless opcode group
RAMTRAP
RAMTRAP
JSRII
JSRIS
CONVERT
31
ROMTRAP
-- used by Swat,
the
debugger
RAMTRAP
ACDEST,
F2=
l3B,
causes
(IR[3-4]
XOR
3)
to
be
used
as
the
low-order two bits
of
the
RSELECT
field. This
addresses the accumulators from the destination field
of
the instruction. The selected register may
be
loaded
or
read.
The emulator has two additional bits
of
state, the
SKIP
and
CARRY
flip flops.
CARRY
is
distinct from
the
microprocessor's
ALUCO
bit, tested by the
ALUCY
function.
CARRY
is set
or
cleared as a function
of
IR
and
many other things (see section 3.1) when the
DNS~
(do novel shifts,F2=12B) function is executed.
In
particular,
if
IR[12]
is true,
CARRY
will not change.
DNS
also addresses R from (3-IR[3-4]), causes a store
into
Runless
IR[12]
is set,
and
sets the
SKIP
flip flop
if
appropriate (see section 3.1).
The
emulator
microcode increments
PC
by 1
at
the beginning
of
the next emulated instruction
if
SKIP
is set, using
BUS+SKIP
(ALUF=13B).
IR~
clears
SKIP
.
. Note
that
the functions which replace the low bits
of
RSELECT
with
IR
affect only the selection
of
R;
they
do
not
affect the address supplied to the constant
ROM.
Two additional emulator specific functions,
BUSODD
(F2=
lOB)
and
MAGIC
(F2= llB), are
not
peculiar
to
emulation,
but
are included for their general usefulness.
BUSODD
merges Bus[lS] into
NEXT[9].
MAGIC
is
a modifier applied to L
LSH
1
and
L
RSH
1 to allow double length shifts. L
LSH
1
and
L
RSH
1 normally
shift zero into the vacated bit position in the shifter output.
MAGIC
places the high order
bit
of
T
into
the low order bit
of
the shifter output on left shifts, and places the
.low
order bit
of
T into
the
high
order
bit position
of
the. shifter output on right shifts. (The microassembler accepts L
MLSH
1 to specify
the
combination
of
L
LSH
1 and
MAGIC,
and
similarly for L
MRSH
1.)
The
STARTF
function (Fl=17B) is generated by the
SIO
instruction, and is used to define commands for
I/O
hardware, including the Ethernet.
The
RSNF
function (F1=16B) is decoded by the Ethernet interface, which gates the host address wired
on
the backplane onto
Bus[8-1S].
Bus[O-7]
is
not
driven and will therefore
be
-1.
If
no
Ethernet interface is
present,
BUS
will
be
-1.
.
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