Hitachi L32S02A User Manual

IC Block Diagram
-25-
ADTRG(P53)
A
N0
To An 3
P50 TO P53)
AVCC,AVSS
10-bit4-ch
AD
converter
CPU(TLCS-900/L1)
XWA W A
XBC B C
XDE D E
XHL H L
XIX IX
XIY IY
XIZ IZ
XSP SP
32 bits
High-speed
oscillator
DVCC
DVSS
X1
X2
Clock gear
Low speed
oscillator
XT1(P96)
XT2(P97)
RESET
Am0
Am1
ALE
SR F
PC
TXD0(P90)
RXD0(P91)
SCLK0/CTSO(P92)
SIO/UART
(Channel/0)
P00 to P07)
AD0 to Ad7
P10 to P17)
Ad8 A8 to AD15/A15
P20 to P25)
A0 A16 to A5/A21
Port0
Port3
Port6
Port2
Port9
Port1
SCK(P60)
SO/SDA(P61)
SI/SCL(P62)
Serial bus
interface
(SBI)
Watchdog
timer
(WDT)
TA01N(P70)
TA1OUT(P71)
8-bit timer
(TMRA 0)
8-bit timer
(TMRA 1)
8-bit timer
(TMRA 2)
8-bit timer
(TMRA 3)
8-bit timer
(TMRA 4)
8-bit timer
(TMRA 5)
16-bit timer
(TMRB0)
RTC
10-Kbyte RAM
P40 to P42)
cs0tocs2
CS/WAIT
controller
(4 blocks)
RD(P30)
WR(P31)
HWR(P32)
P93
P94
P95
TA3OUT(P72)
TA5OUT(P74)
TA41N(P73)
Interrupt
controller
NMI
INT0(P63)
TB0IN0/INT5(P80)
TB0IN1/INT5(P81)
TB0OUT0(P82)
TB0OUT1(P83)
T5BS4-9999 Block Diagram
U4
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Hitachi L32S02A Specifications

General

Brand	Hitachi
Model	L32S02A
Category	LCD TV
Language	English