IBM 5150 Technical Reference

signal the microprocessor with an interrupt. There are three
conditions that will disable the coprocessor interrupt to the
microprocessor:
1. Exception and interrupt-enable bits of the control word are set
to
l's.
2. System-board switch-block 1, switch 2, set in the On position.
3. Non-maskable interrupt (NMI) register
(REG) is set to zero.
At power-on time, the NMI REG is cleared to disable the NMI.
Any program using the coprocessor's interrupt capability must
ensure that conditions 2 and 3 are never met during the operation
of the software or an "Endless WAIT" will occur.
An "Endless
WAIT" will have the microprocessor waiting for the
'not busy'
signal from the coprocessor while the coprocessor
is waiting for
the microprocessor to interrupt.
Because a memory parity error may also cause an interrupt to the
microprocessor NMI line, the program should check the
coprocessor status for an exception condition.
If a coprocessor
~ exception condition is not found, control should be passed to the
normal NMI handler.
If an 8087 exception condition is found,
the program may clear the exception by executing the FNSA VE
or the
FNCLEX instruction, and the exception can be identified
and acted upon.
The NMI
REG and the coprocessor's interrupt are tied to the
NMI line through the NMI interrupt logic. Minor modifications
to programs designed for use with a coprocessor must be made
before the programs will be compatible with the IBM Personal
Computer
Math Coprocessor.
Coprocessor 2-5

IBM 5150 Specifications

General

Brand	IBM
Model	5150
Category	Desktop
Language	English