IBM Personal System/2 65 SX User Manual

The
ROM
enable
bit
in
System-Board
POS
Register
5
(hex
0105)
controls
ROM
or
RAM
access
at
address
space
hex
0E0000
to
OFFFFF.
When
enabled,
ROM
is
not
parity-checked
and
operates
with
three
62.5-nanosecond
wait
states.
RAM Subsystem
The
RAM
subsystem
on
the
system
board
starts
at
address
hex
000000
of
the
address
space.
The
RAM
subsystem
is
18
bits
wide:
16
data
bits
and
2
parity
bits.
One
parity
bit
is
generated
for
each
byte
of
data
written.
During
a
read
operation,
one
parity
bit
is
checked
for
each
byte
of
data
read
by
the
device
controlling
the
bus.
The
system
board
contains
two
72-pin
memory
connectors.
Each
connector
can
support
1MB,
2MB,
or
4MB
of
memory.
The
system
enables
and
disables
memory
in
1MB
blocks.
Each
1MB
block
must
Start
on
a
1MB
boundary.
Because
128KB
of
I/O
ROM,
128KB
of
system-board
ROM,
and
128KB
of
video
memory
are
mapped
within
the
first
1MB
of
address
space,
the
first
physical
1MB
of
RAM
cannot
be
mapped
to
contiguous
addresses
and
is
therefore
split
at
the
640KB
boundary,
creating
a
384KB
overflow.
The
high
128KB
of
the
overflow
is
mapped
to
the
system-board
ROM
address
space;
the
remaining
256KB,
called
the
split-memory
block,
is
either
disabled
or
mapped
to
the
first
available
address
following
the
last
full
1MB
of
activated
system-board
memory.
Split-memory-block
remapping
and
disabling
are
controlled
by
System-Board
POS
Register
5
(hex
0105).
Additional
memory
can
be
added
in
any
of
the
micro
channel
connectors.
The
total
amount
of
memory
installed
must
not
exceed
the
16MB
addressing
limit.
The
total
amount
of
usable
memory
is
less
than
the
amount
of
memory
installed
because
of
ROM-to-RAM
remapping
and
split-memory-block
remapping.
3-8
Model
65
System
Board
—
October
1990

IBM Personal System/2 65 SX Specifications

General

Brand	IBM
Model	Personal System/2 65 SX
Category	Desktop
Language	English