IBM Personal System/2 65 SX User Manual

Central-Arbiter Programming
The central-arbitration control point provides access to
programmable options through the Arbitration register, which is
accessed at I/O address hex 0090. The bit definitions are different for
read and write operations, as shown in the following tables.
Bit Definition
7 Enable System-Microprocessor Cycle
6 Arbitration Mask
5 Enable Extended Arbitration (Not Supported)
4-0 Reserved
Figure 93-2. Arbitration Register, Write to Hex 0090
Bit Definition
7 Enable System-Microprocessor Cycle
6 Arbitration Masked by NMI
5 Bus Time-Out
4 Reserved
3-0 Value of Arbitration Bus during Previous Grant State
Figure 3-3. Arbitration Register, Read Hex 0090
Bit7 When set to 1, this bit enables system-microprocessor
cycles during arbitration cycles. This bit can be set to 0 if
an arbitrating device requires total control of the channel
bandwidth. This bit is set to 0 by a system reset.
Reading this bit as a 1 indicates system-microprocessor
cycles are enabled during arbitration.
BIt6 When set to 1, this bit causes the central-arbitration
control point to enter the arbitration state. The system
microprocessor controls the channel until this bit is reset
to 0. This bit is set to 0 by a system reset.
Reading this bit as a 1 indicates that an NMI has occurred
and has masked arbitration.
Warning: This bit should be set to 1 only by diagnostic
routines and system error-recovery routines.
Bits When set to 1, this bit extends the arbitration cycle from a
minimum of 400 nanoseconds to a minimum of 800
nanoseconds. The Model 65 SX does not support this
mode of operation. When set to 1, this bit can cause
unpredictable results.
Model 65 System Board — October 1990 3-5

IBM Personal System/2 65 SX Specifications

General

Brand	IBM
Model	Personal System/2 65 SX
Category	Desktop
Language	English