IBM Personal System/2 65 SX User Manual

Warning: The operation following a write to hex 0070 should access
hex 0071; otherwise, intermittent malfunctions and unreliable
operation of the RT/CMOS RAM can occur.
Bit7 When this bit is set to 1, the NMI is masked off (disabled).
This bit is set to 1 by a power-on reset. This is a
write-only bit.
Bit6 This bit is reserved.
Bits5-0 These bits are used to select RT/CMOS RAM addresses.
RT/CMOS Data Register (Hex 0071)
This register is used in conjunction with the RT/CMOS Address and
NMI Mask register (hex 0070) to read from and write to the RT/CMOS
RAM bytes.
Bit Function
7-0 RT/CMOS Data
Figure 3-9. RTICMOS Data Register (Hex 0071)
RT/CMOS RAM I/O Operations
During I/O operations to the RT/GMOS RAM addresses, interrupts
should be masked to prevent other interrupt routines from changing
the RT/CMOS Address register before data is read or written. After
1/O operations, the RT/CMOS Address and NMI Mask register (hex
0070) should be left pointing to Status Register D (hex OOD).
Warning: The operation following a write to hex 0070 should access
hex 0071; otherwise, intermittent malfunctions and unreliable
operation of the RT/CMOS RAM can occur.
Writing to the RT/CMOS RAM requires the foilowing steps:
1. Write the RT/CMOS RAM address to the RT/CMOS Address and
NMI Mask register (hex 0070).
2. Write the data to the RT/CMOS Data register (hex 0071).
Reading from the RT/CMOS RAM requires the following steps:
1. Write the RT/CMOS RAM address to the RT/CMOS and NMI Mask
register (hex 0070).
2. Read the data from the RT/CMOS Data register (hex 0071).
Model 65 System Board — October 1990 3-13

IBM Personal System/2 65 SX Specifications

General

Brand	IBM
Model	Personal System/2 65 SX
Category	Desktop
Language	English