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NXP Semiconductors MPC5566 User Manual
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©
Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor
MPC5566RM
Rev. 2.1, 05/2012
This MPC5566 Reference Manual set c
onsists of the following files:
•
MPC5566 Reference Manual Addendum, Rev 2
•
MPC5566 Microcontroller Reference Manual, Rev 2
MPC5566 Microcontroller
Ref
erence Man
ual
2
Table of Contents
Table of Contents
8
MPC5566 Reference Manual
2
MPC5566 Reference Manual Addendum, Rev
4
Table of Contents
8
Chapter 1 Introduction
14
Chapter 3 E200Z6 Core Complex
23
Default Chapter
58
MPC5566 Microcontroller Reference Manual, Rev
58
Rev.
59
Rev.
60
Features
61
MPC5500 Family Comparison
68
Detailed Features
69
Chapter 1
71
System Bus Crossbar Switch (XBAR)
71
Frequency Modulated Phase-Locking Loop (FMPLL)
72
Cache
73
Enhanced Management Input/Output System (Emios)
74
Enhanced Serial Communications Interface (Esci)
75
Chapter 14
76
Chapter 15
76
Fast Ethernet Controller (FEC)
76
MPC5500 Family Memory Map
77
Multi-Master Operation Memory Map
79
Block Diagram
82
Figure 2-1. Mpc5566 Signals
83
Default Chapter
84
External Signal Descriptions
84
Chapter 2
85
Device Signals Summary
85
Cal_Addr[8]_Cal_Cs
88
Cal_Addr[9]_Cal_Cs
88
Reset
88
Cal_Data[0:15]
88
Cal_Oe
88
Cal_Rd_Wr
88
Cal_Ts
89
Evti
89
Evto
89
Gpio
89
Gpio[206:207]
89
Mcko
89
Mdo[3:0]
89
Mseo[1:0]
89
Rdy
89
Detailed Signal Description
99
Reset and Configuration Signals
100
Rstcfg_Gpio[210]
101
External Address / Master Address Expansion / GPIO ADDR[30:31]_ADDR[6:7]_GPIO[26:27]
102
Data[22]_Fec_Rxd[0]_Gpio[50]
103
Data[30]_Fec_Rxd[2]_Gpio[58]
104
Tea_Fec_Rxd[3]_Gpio[71]
105
Mdo[0]
106
Cnrxa_Rxda_Gpio
107
Cnrxb_Pcsc[4]_Gpio[86
107
Cntxa_Txda_Gpio
107
Cntxb_Pcsc[3]_Gpio[85
107
Cntxc_Pcsd[3]_Gpio[87
107
Jcomp
107
Cnrxc_Pcsd[4]_Gpio[88
108
Rxda_Gpio
108
Rxdb_Pcsd[5]_Gpio[92
108
Scka_Pcsc[1]_Gpio[93
108
Sina_Pcsc[2]_Gpio[94
108
Txda_Gpio
108
Txdb_Pcsd[1]_Gpio[91
108
Pcsa[0]_Pcsd[2]_Gpio[96
109
Pcsa[1]_Pcsb[2]_Gpio[97
109
Pcsa[2]_Sckd_Gpio[98
109
Pcsa[3]_Sind_Gpio[99
109
Pcsa[4]_Soutd_Gpio[100
109
Pcsa[5]_Pcsb[3]_Gpio[101
109
Souta_Pcsc[5]_Gpio[95
109
Pcsb[0]_Pcsd[2]_Gpio[105
110
Pcsb[1]_Pcsd[0]_Gpio[106
110
Pcsb[2]_Soutc_Gpio[107
110
Pcsb[3]_Sinc_Gpio[108
110
Sckb_Pcsc[1]_Gpio[102
110
Sinb_Pcsc[2]_Gpio[103
110
Soutb_Pcsc[5]_Gpio[104
110
Pcsb[4]_Sckc_Gpio[109
111
Pcsb[5]_Pcsc[0]_Gpio[110
111
An[5]_Dan2–
112
An[12]_Ma[0]_Sds
113
Tcrclka_Irq[7]_Gpio[113
114
An[16:39]
114
Etpua[0]_Etpua[12]_Gpio[114]
115
Etpua[12:15]_Pcsb[1:5]_Gpio[126:129]
116
Etpua[6]_Etpua[18]_Gpio[120]
116
Etpua[16:19]_Pcsd[1:4]_Gpio[130:133]
117
Etpua[20:23]_Irq[8:11]_Gpio[134:137]
117
Etpua[13]_Pcsb[3]_Gpio[127]
117
Etpua[24:27]_Irq[12:15]_Gpio[138:141]
118
Etpua[28:29]_Pcsc[1:2]_Gpio[142:143]
118
Etpua[30:31]_Pcsc[3:4]_Gpio[144:145]
118
Etpua[21]_Irq[9]_Gpio[135]
118
Emios[0:9]_Etpua[0:9]_Gpio[179:188]
119
Emios[10:11]_Pcsd[3:4]_Gpio[189:190]
119
Emios[12]_Soutc_Gpio[191
119
Etpub[0:15]_Etpub[16:31]_Gpio[147:162]
119
Etpub[16]_Pcsa[1]_Gpio
119
Tcrclkb_Irq[6]_Gpio[146
119
Emios[13]_Soutd_Gpio[192
120
Emios[14]_Irq[0]_Cntxd_Gpio[193
120
Emios[15]_Irq[1]_Cnrxd_Gpio[194
120
Emios Channel /Etpu B Output Channel / GPIO EMIOS[20:21]_ETPUB[4:5]_GPIO[199:200]
121
Calibration Bus Signals
122
Cal_Ts
123
Extal_Extclk
123
Xtal
123
Vddan
124
Clkout Engclk
125
Vddehn
125
Etpu Pin Connections and Serialization
128
Etpua[16:31]
129
Etpub[0:31]
131
Emios Pin Connections and Serialization
133
Introduction
136
Block Diagram
137
Overview
138
Chapter 3
139
Instruction Unit Features
139
MMU Features
140
Core Registers and Programmer's Model
141
Power Architecture Registers
144
Supervisor-Level Only Registers
145
Core-Specific Registers
147
E200Z6 Core Complex Features Not Supported in the Device
148
Functional Description
149
Translation Flow
150
Effective to Real Address Translation
151
MMU Assist Registers (MAS[0:4], MAS[6])
152
MAS[1] Register
153
MAS[2] Register
154
MAS[3] Register
155
MAS[6] Register
156
L1 Cache
157
Cache Organization
158
Cache Line Replacement Algorithm
160
L1 Cache Control and Status Register 0 (L1CSR0)
161
L1 Cache Configuration Register 0 (L1CFG0)
164
Interrupt Types
165
Bus Interface Unit (BIU)
167
Signal Processing Extension APU (SPE APU)
168
External References
169
Introduction
170
External Signal Description
171
Chapter 4
172
Reset Configuration (RSTCFG)
172
System Reset Control Register (SIU_SRCR)
174
Functional Description
175
Reset Sources
176
External Reset
177
Loss-Of-Clock Reset
178
Checkstop Reset
179
Software System Reset
180
RSTCFG Pin
181
PLLCFG[0:1] Pins
182
Invalid RCHW
184
Reset Configuration Timing
185
Reset Flow
187
Introduction
190
Features
192
External Signal Description
193
Master Privilege Control Register (Pbridge_X_Mpcr)
194
Chapter 5 Ripheral Access Control Registers (Pbridge_X_Opacr)
196
Functional Description
201
Read Cycles
202
Introduction
204
Overview
206
Detailed Signal Descriptions
207
Reset Output (RSTOUT)
208
I/O Weak Pullup Reset Configuration (WKPCFG)
209
External Interrupts
210
Edge-Detect Events
211
Register Descriptions
212
MCU ID Register (SIU_MIDR)
213
Reset Status Register (SIU_RSR)
214
System Reset Control Register (SIU_SRCR)
217
External Interrupt Status Register (SIU_EISR)
218
DMA Interrupt Request Enable Register (SIU_DIRER)
219
Dma/Interrupt Request Select Register (SIU_DIRSR)
220
Overrun Status Register (SIU_OSR)
221
Overrun Request Enable Register (SIU_ORER)
222
IRQ Rising-Edge Event Enable Register (SIU_IREER)
223
IRQ Digital Filter Register (SIU_IDFR)
224
Pad Configuration Registers (SIU_PCR)
225
Pad Configuration Register 0 (SIU_PCR0)
227
Pad Configuration Registers 1–3 (SIU_PCR1–SIU_PCR3)
228
Pad Configuration Registers 4–7 (SIU_PCR4–SIU_PCR7)
229
Pad Configuration Registers 23–25 (SIU_PCR23–SIU_PCR25)
230
Pad Configuration Registers 26–27 (SIU_PCR26–SIU_PCR27)
231
Pad Configuration Registers 44 (SIU_PCR44)
232
Pad Configuration Registers 47 (SIU_PCR47)
233
Pad Configuration Registers 49 (SIU_PCR49)
234
Pad Configuration Registers 51 (SIU_PCR51)
235
Pad Configuration Registers 52 (SIU_PCR52)
236
Pad Configuration Registers 54 (SIU_PCR54)
237
Pad Configuration Registers 55 (SIU_PCR55)
238
Pad Configuration Registers 57 (SIU_PCR57)
239
Pad Configuration Registers 58 (SIU_PCR58)
240
Pad Configuration Registers 60–61 (SIU_PCR60–SIU_PCR61)
241
Pad Configuration Register 62 (SIU_PCR62)
242
Pad Configuration Registers 64–65 (SIU_PCR64–SIU_PCR65)
243
Pad Configuration Register 68 (SIU_PCR68)
244
Pad Configuration Register 70 (SIU_PCR70)
245
Pad Configuration Register 72 (SIU_PCR72)
246
Pad Configuration Register 73 (SIU_PCR73)
247
Pad Configuration Register 82–75 (SIU_PCR82–SIU_PCR75)
248
Pad Configuration Register 84 (SIU_PCR84)
249
Pad Configuration Register 86 (SIU_PCR86)
250
Pad Configuration Register 87 (SIU_PCR87)
251
Pad Configuration Register 89 (SIU_PCR89)
252
Pad Configuration Register 91 (SIU_PCR91)
253
Pad Configuration Register 93 (SIU_PCR93)
254
Pad Configuration Register 94 (SIU_PCR94)
255
Pad Configuration Registers 96 (SIU_PCR96)
256
Pad Configuration Registers 97 (SIU_PCR97)
257
Pad Configuration Register 99 (SIU_PCR99)
258
Pad Configuration Register 100 (SIU_PCR100)
259
Pad Configuration Register 102 (SIU_PCR102)
260
Pad Configuration Register 103 (SIU_PCR103)
261
Pad Configuration Register 105 (SIU_PCR105)
262
Pad Configuration Register 106 (SIU_PCR106)
263
Pad Configuration Register 108 (SIU_PCR108)
264
Pad Configuration Register 109 (SIU_PCR109)
265
Pad Configuration Registers 111–112 (SIU_PCR111–SIU_PCR112)
266
Pad Configuration Register 114–117 (SIU_PCR114–SIU_PCR117)
267
Pad Configuration Register 118 (SIU_PCR118)
268
Pad Configuration Register 120 (SIU_PCR120)
269
Pad Configuration Register 121 (SIU_PCR121)
270
Pad Configuration Registers 122–124 (SIU_PCR122–SIU_PCR124)
271
Pad Configuration Register 126 (SIU_PCR126)
272
Pad Configuration Registers 127–129 (SIU_PCR127–SIU_PCR129)
273
Pad Configuration Register 134 (SIU_PCR134)
274
Pad Configuration Register 135 (SIU_PCR135)
275
Pad Configuration Register 137 (SIU_PCR137)
276
Pad Configuration Registers 138–141 (SIU_PCR138–SIU_PCR141)
277
Pad Configuration Register 145 (SIU_PCR145)
278
Pad Configuration Registers 147–162 (SIU_PCR147–SIU_PCR162)
279
Pad Configuration Registers 163 (SIU_PCR163–SIU_PCR166)
280
Pad Configuration Registers 167–178 (SIU_PCR167–SIU_PCR178)
281
Pad Configuration Register 189–190 (SIU_PCR189–SIU_PCR190)
282
Pad Configuration Register 191 (SIU_PCR191)
283
Pad Configuration Register 193 (SIU_PCR193)
284
Pad Configuration Register 194 (SIU_PCR194)
285
Pad Configuration Register 196 (SIU_PCR196)
286
Pad Configuration Register 197 (SIU_PCR197)
287
Pad Configuration Registers 199–200 (SIU_PCR199–SIU_PCR200)
288
Pad Configuration Register 201 (SIU_PCR201)
289
Pad Configuration Registers 203–204 (SIU_PCR203–SIU_PCR204)
290
Pad Configuration Registers 206–207 (SIU_PCR206–SIU_PCR207)
291
Pad Configuration Register 208 (SIU_PCR208)
292
Pad Configuration Register 210 (SIU_PCR210)
293
Pad Configuration Registers 211–212 (SIU_PCR211–SIU_PCR212)
294
Pad Configuration Register 214 (SIU_PCR214)
295
Pad Configuration Register 216 (SIU_PCR216)
296
Pad Configuration Register 218 (SIU_PCR218)
297
Pad Configuration Register 225–224 (SIU_PCR225–SIU_PCR224)
298
Pad Configuration Register 229 (SIU_PCR229)
299
Pad Configuration Registers 257–258 (SIU_PCR257–SIU_PCR258)
300
Pad Configuration Register 261 (SIU_PCR261)
301
Pad Configuration Register 262 (SIU_PCR262)
302
Pad Configuration Register 265 (SIU_PCR265)
303
Pad Configuration Register 267 (SIU_PCR267)
304
Pad Configuration Registers 270–271 (SIU_PCR270–SIU_PCR271)
305
Pad Configuration Register 275 (SIU_PCR275)
306
Pad Configuration Register 278–293 (SIU_PCR278–SIU_PCR293)
307
Pad Configuration Register 295–296 (SIU_PCR295–SIU_PCR296)
308
Pad Configuration Register 299 (SIU_PCR299)
309
GPIO Pin Data Input Registers 0–213 (Siu_Gpdin)
310
Eqadc Trigger Input Select Register (SIU_ETISR)
311
External IRQ Input Select Register (SIU_EIISR)
313
DSPI Input Select Register (SIU_DISR)
315
Chip Configuration Register (SIU_CCR)
318
External Clock Control Register (SIU_ECCR)
319
Compare a Register High (SIU_CARH)
320
Compare a Register Low (SIU_CARL)
321
Compare B Register High (SIU_CBRH)
322
Boot Configuration
323
Reset Control
324
GPIO Operation
325
Eqadc External Trigger Input Multiplexing
326
SIU External Interrupt Input Multiplexing
327
Introduction
332
Overview
333
Modes of Operation
334
Register Descriptions
335
Master Ports
340
Priority Assignment
341
Parking
342
Introduction
344
Memory Map and Register Definition
345
Chapter 7 Slave General-Purpose Control Registers (Xbar_Sgpcrn)
337
Functional Description
339
8.2.1 Register Descriptions
346
Default Chapter
346
Register Descriptions
346
ECC Configuration Register (ECSM_ECR)
347
ECC Status Register (ECSM_ESR)
347
ECC Error Generation Register (ECSM_EEGR)
348
Flash ECC Address Register (ECSM_FEAR)
350
Flash ECC Attributes Register (ECSM_FEAT)
351
Flash ECC Data High Register (ECSM_FEDRH)
352
Flash ECC Data Low Registers (ECSM_FEDRL)
353
RAM ECC Address Register (ECSM_REAR)
354
RAM ECC Master Number Register (ECSM_REMR)
355
RAM ECC Data High Register (ECSM_REDRH)
356
RAM ECC Data Low Registers (ECSM_REDRL)
357
Initialization and Application Information
358
Introduction
362
Features
363
Modes of Operation
364
Memory Map and Register Definition
365
Register Descriptions
369
Chapter 9
371
Flash ECC Master Number Register (ECSM_FEMR)
351
Edma Error Status Register (EDMA_ESR)
371
Edma Enable Request Registers (EDMA_ERQRH, EDMA_ERQRL)
373
Edma Enable Error Interrupt Registers (EDMA_EEIRH, EDMA_EEIRL)
375
Edma Set Enable Request Register (EDMA_SERQR)
376
Edma Set Enable Error Interrupt Register (EDMA_SEEIR)
377
Edma Clear Interrupt Request Register (EDMA_CIRQR)
378
Edma Set START Bit Register (EDMA_SSBR)
379
Edma Interrupt Request Registers (EDMA_IRQRH, EDMA_IRQRL)
380
Edma Error Registers (EDMA_ERH, EDMA_ERL)
381
DMA Hardware Request Status (EDMA_HRSH, EDMA_HRSL)
383
Edma Channel N Priority Registers (Edma_Cprn)
384
Transfer Control Descriptor (TCD)
385
Functional Description
393
Edma Basic Data Flow
394
Edma Performance
397
Initialization and Application Information
400
DMA Programming Errors
402
DMA Request Assignments
403
DMA Arbitration Mode Considerations
406
Fixed-Group Arbitration, Round-Robin Channel Arbitration
407
Multiple Requests
408
Modulo Feature
410
Active Channel TCD Reads
411
Dynamic Programming
413
Introduction
414
Overview
415
Features
417
Modes of Operation
418
Hardware Vector Mode
419
External Signal Description
420
Intc_Cpr
422
Memory Map and Register Definition
422
Register Descriptions
423
Chapter 10
424
INTC Current Priority Register (INTC_CPR)
424
INTC End-Of-Interrupt Register (INTC_EOIR)
426
INTC Priority Select Registers (INTC_PSR0–329)
427
Functional Description
428
Peripheral Interrupt Requests
441
Unique Vector for each Interrupt Request Source
442
Vector Encoder Submodule
443
Details on Handshaking with Processor
444
INTVEC in INTC_IACKR
445
Hardware Vector Mode Handshaking
445
Read INTC_IACKR
445
Write INTC_EOIR
445
Initialization and Application Information
446
Software Vector Mode
447
Hardware Vector Mode
448
Order of Execution
449
Priority Ceiling Protocol
450
And Deadlines
451
Scheduling an ISR on Another Processor
452
Negating an Interrupt Request Outside of Its ISR
453
Intc_Cpr
454
Introduction
456
FMPLL and Clock Architecture
457
FMPLL Bypass Mode
458
FMPLL External Reference Mode
459
FMPLL Crystal Reference Mode Without FM
460
FMPLL Crystal Reference Mode with FM
461
FMPLL Dual-Controller Mode (1:1)
462
Overview
463
FMPLL Modes of Operation
464
External Reference Mode
465
Bypass Mode
466
External Signal Description
467
Synthesizer Status Register (FMPLL_SYNSR)
471
Functional Description
474
Software Controlled Power Management/Clock Gating
475
External Bus Clock (CLKOUT)
476
Clock Operation
477
FMPLL Loss-Of-Lock Reset
478
Loss-Of-Clock Reset
479
Programming System Clock Frequency Without Frequency Modulation
480
Programming System Clock Frequency with Frequency Modulation
482
FM Calibration Routine
484
Introduction
488
Overview
489
Features
490
Modes of Operation
491
Module Disable Mode
492
Debug Mode
493
Detailed Signal Descriptions
494
Chapter 12
495
Burst Data in Progress (BDIP)
495
Transfer Acknowledge (TA)
496
Bus Busy (BB)
497
Transfer Size 0 through 1 (TSIZ[0:1])
498
Signal Function and Direction by Mode
499
Memory Map and Register Definition
500
Register Descriptions
501
EBI Transfer Error Status Register (EBI_TESR)
503
EBI Bus Monitor Control Register (EBI_BMCR)
504
EBI Base Registers 0–3 (Ebi_Brn and EBI Calibration Base Registers 0–3 (Ebi_Cal_Brn)
505
EBI Option Registers 0–3 (Ebi_Orn) and EBI Calibration Option Registers
507
Functional Description
508
Memory Controller with Support for Various Memory Types
509
Burst Support (Wrapped Only)
510
Port Size Configuration Per Chip Select (16 or 32 Bits)
511
Configurable Bus Speed Clock Modes
512
Misaligned Access Support
513
External Bus Operations
514
External Clocking
515
Single-Beat Transfer
516
Single-Beat Write Flow
519
Back-To-Back Accesses
521
Burst Transfer
525
Small Access Example #3: 32-Byte Read to 32-Bit Port with
526
TBDIP Effect on Burst Transfer
529
Small Accesses (Small Port Size and Short Burst Length)
530
Small Access Example #1: 32-Bit Write to 16-Bit Port
532
Size, Alignment, and Packaging on Transfers
534
Arbitration
537
External (or Central) Bus Arbiter
538
Internal Bus Arbiter
539
Termination Signals Protocol
543
Bus Operation in External Master Mode
546
Address Decoding for External Master Accesses
547
Bus Transfers Initiated by an External Master
548
Bus Transfers Initiated by the EBI in External Master Mode
553
Back-To-Back Transfers in External Master Mode
554
Non-Chip-Select Burst in 16-Bit Data Bus Mode
557
Calibration Bus Operation
559
Initialization and Application Information
560
Running with Asynchronous Memories
561
Timing and Connections for Asynchronous Memories
562
Connecting an MCU to Multiple Memories
564
Introduction
566
Features
568
External Signal Description
569
Flash Memory Map
571
Register Descriptions
574
Chapter 13 MCR Simultaneous Register Writes
577
Low/MID Address Space Block Locking Register (FLASH_LMLR)
578
High Address Space Block Locking Register (FLASH_HLR)
580
Low/MID Address Space Block Select Register (FLASH_LMSR)
582
High Address Space Block Select Register (FLASH_HSR)
583
Flash Bus Interface Unit Control Register (FLASH_BIUCR)
584
Flash Bus Interface Unit Access Protection Register (FLASH_BIUAPR)
587
FBIU Basic Interface Protocol
588
FBIU Line Read Buffers and Prefetch Operation
589
FBIU Per-Master Prefetch Triggering
590
Read While Write (RWW)
591
Software Locking
595
Flash Erase Suspend/Resume
596
Flash Shadow Block
599
Flash Disable
600
FLASH_BIUAPR Modification
601
Flash Memory Array: Reset
602
Introduction
604
Register Memory Map
605
Access Timing
606
Reset Effects on SRAM Accesses
607
Example Code
608
Introduction
610
Overview
612
Features
613
Interface Options
614
Top Level Module Memory Map
615
Registers
618
FEC Registers
620
Ethernet Interrupt Mask Register (EIMR)
621
Receive Descriptor Active Register (RDAR)
622
Transmit Descriptor Active Register (TDAR)
623
Ethernet Control Register (ECR)
624
MII Management Frame Register (MMFR)
625
MII Speed Control Register (MSCR)
626
MIB Control Register (MIBC)
627
Receive Control Register (RCR)
628
Transmit Control Register (TCR)
630
Physical Address Low Register (PALR)
631
Physical Address Upper Register (PAUR)
632
Descriptor Individual Upper Address Register (IAUR)
633
Descriptor Individual Lower Address (IALR)
634
Descriptor Group Upper Address (GAUR)
635
FIFO Transmit FIFO Watermark Register (TFWR)
636
FIFO Receive Bound Register (FRBR)
637
Receive Descriptor Ring Start (ERDSR)
638
Transmit Buffer Descriptor Ring Start (ETDSR)
639
Initialization Sequence
640
Application Initialization (Prior to Asserting ECR[ETHER_EN])
641
Microcontroller Initialization
642
FEC Frame Transmission
643
FEC Frame Reception
644
Ethernet Address Recognition
645
Hash Algorithm
647
Full Duplex Flow Control
650
Inter-Packet Gap (IPG) Time
651
Ethernet Error-Handling Procedure
652
Reception Errors
653
Driver/Dma Operation with Transmit Bds
654
Ethernet Receive Buffer Descriptor (Rxbd)
655
Ethernet Transmit Buffer Descriptor (Txbd)
657
Introduction
660
Features
661
Serial Boot Mode
662
BAM Program Operation
663
Chapter 16
666
Internal Boot Mode
666
External Boot Modes
667
Single Bus Master or Multiple Bus Masters
668
Read the Reset Configuration Halfword
670
Serial Boot Mode Flexcan and Esci Configuration
671
Download Process for Flexcan Serial Boot Mode
673
Esci Serial Boot Mode Download Process
676
Interrupts
678
Introduction
680
Chapter 22
682
Overview
682
Chapter 17 Emios Operating Modes
683
External Signal Description
684
Output Disable Input—Emios Output Disable Input Signals
685
Register Description
687
Emios Global Flag Register (EMIOS_GFR)
688
Emios Output Update Disable Register (EMIOS_OUDR)
689
Emios Channel a Data Register (Emios_Cadrn)
690
Emios Channel Counter Register (Emios_Ccntrn)
692
Emios Channel Status Register (Emios_Csrn)
700
Emios Alternate Address Register (Emios_Altan)
701
Bus Interface Unit (BIU)
702
Effect of Freeze on the STAC Client Submodule
703
Unified Channel (UC)
704
Programmable Input Filter (PIF)
706
Clock Prescaler (CP)
707
General Purpose Input/Output Mode (GPIO)
708
Single-Action Output Compare Mode (SAOC)
709
Input Pulse-Width Measurement Mode (IPWM)
710
Input Period Measurement Mode (IPM)
712
Double-Action Output Compare Mode (DAOC)
714
Pulse/Edge Accumulation Mode (PEA)
716
Pulse and Edge Counting Mode (PEC)
718
Quadrature Decode Mode (QDEC)
720
Windowed Programmable Time Accumulation Mode (WPTA)
722
Modulus Counter Mode (MC)
723
Output Pulse-Width Modulation Mode (OPWM)
733
Modulus Counter Buffered Mode (MCB)
736
Output Pulse-Width Modulation, Buffered Mode (OPWMB)
750
Initialization/Application Information
754
Introduction
758
Block Diagram
759
Etpu Operation Overview
760
Etpu Engine
761
Chapter 18
762
Etpu Timer Channels
762
Shared Data Memory (SDM)
763
Task Scheduler
764
Microengine
765
Modes of Operation
767
User Configuration Mode
768
Output and Input Channel Signals
769
Time Base Clock Signal (TCRCLKA and TCRCLKB)
770
Memory Map and Register Definition
771
Etpu Register Addresses
772
System Configuration Registers
775
Etpu Coherent Dual-Parameter Controller Register (ETPU_CDCR)
777
Etpu MISC Compare Register (ETPU_MISCCMPR)
779
Etpu Engine Configuration Register (ETPU_ECR)
780
Time Base Registers
783
Etpu Time Base Configuration Register (ETPU_TBCR)
784
Etpu Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)
787
Etpu Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)
788
STAC Bus Configuration Register (ETPU_REDCR)
789
Global Channel Registers
790
Etpu Channel Data Transfer Request Status Register (ETPU_CDTRSR)
791
Etpu Channel Interrupt Overflow Status Register (ETPU_CIOSR)
792
Etpu Channel Interrupt Enable Register (ETPU_CIER)
794
Etpu Channel Data Transfer Request Enable Register (ETPU_CDTRER)
795
Etpu Channel Pending Service Status Register (ETPU_CPSSR)
796
Etpu Channel Service Status Register (ETPU_CSSR)
797
Channel Registers Layout
798
Etpu Channel N Configuration Register (Etpu_Cncr)
799
Etpu Channel N Status Control Register (Etpu_Cnscr)
800
Etpu Channel N Host Service Request Register (Etpu_Cnhsrr)
802
Functional Description
803
Introduction
804
Block Diagram
805
Features
807
Modes of Operation
808
Stop Mode
809
External Signal Description
810
Memory Map and Register Definition
812
Eqadc Register Descriptions
815
Eqadc Null Message Send Format Register (EQADC_NMSFR)
816
Eqadc External Trigger Digital Filter Register (EQADC_ETDFR)
817
Eqadc CFIFO Push Registers 0–5 (Eqadc_Cfprn)
819
Eqadc Result FIFO Pop Registers 0–5 (Eqadc_Rfprn)
820
Eqadc Interrupt and Edma Control Registers 0–5 (Eqadc_Idcrn)
822
Eqadc FIFO and Interrupt Status Registers 0–5 (Eqadc_Fisrn)
825
Eqadc CFIFO Transfer Counter Registers 0–5 (Eqadc_Cftcrn)
829
Eqadc CFIFO Status Register (EQADC_CFSR)
833
Eqadc SSI Control Register (EQADC_SSICR)
834
Eqadc SSI Receive Data Register (EQADC_SSIRDR)
836
Eqadc CFIFO Registers (Eqadc_Cf[0–5]Rn)
837
Eqadc RFIFO Registers (Eqadc_Rf[0–5]Rn)
838
On-Chip ADC Registers
839
Adcn Control Registers (ADC0_CR and ADC1_CR)
840
ADC Time Stamp Control Register (ADC_TSCR)
842
ADC Time Base Counter Registers (ADC_TBCR)
843
Functional Description
845
Data Flow in the Eqadc
846
Assumptions/Requirements Regarding the External Device
848
Command Execution and Result Return
849
Message Formats for On-Chip ADC Operation
850
Message Formats for External Device Operation
858
Command/Result Queues
862
CFIFO Prioritization and Command Transfer
865
External Trigger from Etpu or Emios Channels
869
CFIFO Scan Trigger Modes
870
Single-Scan Mode
871
Continuous-Scan Mode
873
CFIFO Scan Trigger Mode Start/Stop Summary
874
CFIFO and Trigger Status
875
Command Queue Completion Status
877
Pause Status
878
Trigger Overrun Status
879
Result Fifos
885
Distributing Result Data into Rfifos
888
On-Chip ADC Configuration and Control
889
Time Stamp Feature
892
MAC Unit and Operand Data Format
893
ADC Control Logic Overview and Command Execution
894
Internal/External Multiplexing
897
External Multiplexing
899
Eqadc Edma/Interrupt Request
901
Eqadc Synchronous Serial Interface (SSI) Submodule
904
Eqadc SSI Data Transmission Protocol
905
Abort Feature
906
Analog Submodule
909
RSD Overview
910
RSD Adder
911
Initialization of On-Chip Adcs and an External Device
912
Configuring Eqadc for Applications
913
Eqadc/Edma Controller Interface
915
Receive Queue/Rfifo Transfers
916
Sending Immediate Command Setup Example
917
Command Queue and Result Queue Usage
918
ADC Result Calibration
919
MAC Configuration Procedure
920
Example Calculation of Calibration Constants
921
Eqadc Versus QADC
922
Introduction
926
Block Diagram
927
Features
928
Modes of Operation
930
External Signal Description
931
Chapter 20
932
Peripheral Chip Select 4 / Master Trigger (Pcsx[4]_Mtrig)
932
Register Descriptions
933
DSPI Transfer Count Register (Dspix_Tcr)
936
DSPI Clock and Transfer Attributes Registers 0–7 (Dspix_Ctarn)
937
DSPI Status Register (Dspix_Sr)
944
DSPI PUSH TX FIFO Register (Dspix_Pushr)
948
DSPI POP RX FIFO Register (Dspix_Popr)
950
DSPI Transmit FIFO Registers 0–3 (Dspix_Txfrn)
951
DSPI Receive FIFO Registers 0–3 (Dspix_Rxfrn)
952
DSPI DSI Configuration Register (Dspix_Dsicr)
953
DSPI DSI Serialization Data Register (Dspix_Sdr)
955
DSPI DSI Alternate Serialization Data Register (Dspix_Asdr)
956
DSPI DSI Transmit Comparison Register (Dspix_Compr)
957
DSPI DSI Deserialization Data Register (Dspix_Ddr)
958
Modes of Operation
959
Master Mode
960
Debug Mode
961
Serial Peripheral Interface (SPI) Configuration
962
FIFO Disable Operation
963
Draining the TX FIFO
964
Draining the RX FIFO
965
DSI Slave Mode
966
DSI Deserialization
967
Change in Data Control
968
DSPI B Connectivity
969
DSPI C Connectivity
970
DSPI D Connectivity
971
Multiple Transfer Operation (MTO)
972
Internal Muxing and SIU Support for Serial and Parallel Chaining
973
Parallel Chaining
974
Serial Chaining
975
Combined Serial Interface (CSI) Configuration
976
CSI Deserialization
977
DSPI Baud Rate and Clock Delay Generation
978
Peripheral Chip Select Strobe Enable (PCSS)
979
Transfer Formats
980
Classic SPI Transfer Format (CPHA = 0)
982
Classic SPI Transfer Format (CPHA = 1)
983
Modified Transfer Format Enabled (MTFE = 1) with Classic SPI Transfer Format Cleared (CPHA = 0) for SPI and DSI
984
Modified Transfer Format Enabled (MTFE = 1) with Classic SPI Transfer Format Set (CPHA = 1) for SPI and DSI
985
Continuous Selection Format
986
Clock Polarity Switching between DSPI Transfers
988
Interrupts and DMA Requests
990
Transmit FIFO Underflow Interrupt Request (TFUF)
991
Slave Interface Signal Gating
992
Baud Rate Settings
993
Delay Settings
994
Calculation of FIFO Pointer Addresses
995
Entry in the TX FIFO
996
Introduction
998
Overview
999
External Signal Description
1000
Register Descriptions
1001
Esci Control Register 2 (Escix_Cr2)
1004
Esci Data Register (Escix_Dr)
1005
Esci Status Register (Escix_Sr)
1006
LIN Control Register (Escix_Lcr)
1009
LIN Transmit Register (Escix_Ltr)
1010
LIN Receive Register (Escix_Lrr)
1013
LIN CRC Polynomial Register (Escix_Lpr)
1014
Overview
1015
Data Format
1016
Baud Rate Generation
1017
Transmitter
1018
Break Characters
1020
Fast Bit Error Detection in LIN Mode
1021
Receiver
1022
Character Reception
1023
Framing Errors
1025
Slow Data Tolerance
1026
Fast Data Tolerance
1027
Idle Input Line Wake-Up (WAKE = 0)
1028
Loop Operation
1029
Disabling the Esci
1030
Features of the LIN Hardware
1033
Generating an RX Frame
1034
LIN Error Handling
1035
LIN Setup
1036
Introduction
1038
Block Diagram
1039
Features
1040
Modes of Operation
1041
External Signal Description
1042
Memory Map
1043
Message Buffer Structure
1044
Register Descriptions
1046
Module Configuration Register (Canx_Mcr)
1047
Control Register (Canx_Cr)
1049
Free Running Timer (Canx_Timer)
1052
RX Global Mask (Canx_Rxgmask)
1053
RX 14 Mask (Canx_Rx14Mask)
1054
Error Counter Register (Canx_Ecr)
1055
Error and Status Register (Canx_Esr)
1056
Interrupt Masks High Register (Icanx_Imrh)
1059
Interrupt Flags High Register (Canx_Ifrh)
1060
Interrupt Flags Low Register (Canx_Ifrl)
1061
Transmit Process
1062
Receive Process
1063
Reception Queue
1064
Notes on TX Message Buffer Deactivation
1065
CAN Protocol Related Features
1066
Time Stamp
1067
Arbitration and Matching Timing
1069
Module Disabled Mode
1070
Bus Interface
1071
Flexcan2 Addressing and RAM Size
1072
Introduction
1074
External Signal Description
1075
POR Circuits
1076
Chapter 23 V por Circuit
1077
Compatible Power Transistors
1078
Pin Values after por Negates
1080
Introduction
1082
Overview
1083
Chapter 24
1084
IEEE 1149.1-2001 Defined Test Modes
1084
External Signal Description
1085
Bypass Register
1086
Functional Description
1087
Enabling the TAP Controller
1089
BYPASS Instruction
1090
HIGHZ Instruction
1091
Initialization/Application Information
1092
Introduction
1094
Block Diagram
1095
Modes of Operation
1097
Chapter 25
1098
Reduced-Port Mode
1098
Detailed Signal Descriptions
1099
Test Data Input (TDI)
1100
NDI Functional Description
1103
Configuring the NDI for Nexus Messaging
1104
Programmable MCKO Frequency
1105
Nexus Port Controller (NPC)
1106
Register Descriptions
1107
Port Configuration Register (PCR)
1108
NPC Functional Description
1110
Output Messages
1111
Rules of Messages
1112
Enabling the NPC TAP Controller
1113
Retrieving Device IDCODE
1115
Selecting a Nexus Client Register
1116
Nexus Auxiliary Port Sharing
1117
Nexus Reset Control
1118
E200Z6 Class 3 Nexus Module (NZ6C3)
1119
Block Diagram
1120
Overview
1121
Enabling Nexus3 Operation
1122
Tcodes Supported by NZ6C3
1123
NZ6C3 Memory Map and Register Definition
1128
Port Configuration Register (PCR)
1129
Development Control Registers 1 and 2 (DC1, DC2)
1130
Development Status Register (DS)
1132
Read/Write Access Control and Status (RWCS)
1133
Read/Write Access Address (RWA)
1134
Watchpoint Trigger Register (WT)
1135
Data Trace Control Register (DTC)
1136
Data Trace Start Address Registers 1 and 2 (Dtsan)
1137
NZ6C3 Register Access Via JTAG / Once
1138
Ownership Trace
1139
OTM Error Messages
1140
Branch Trace Messaging (BTM)
1141
BTM Using Branch History Messages
1142
BTM Message Formats
1143
Resource Full Messages
1144
Program Correlation Messages
1145
Program Trace Synchronization Messages
1146
BTM Operation
1148
Sequential Instruction Count (I-CNT)
1149
Data Trace
1150
Data Trace Messaging (DTM)
1151
DTM Overflow Error Messages
1152
DTM Operation
1154
Data Trace Timing Diagrams (Eight MDO Configuration)
1155
Watchpoint Support
1156
Watchpoint Error Message
1157
Watchpoint Timing Diagram (2 MDO and 1 MSEO Configuration)
1158
Single Write Access
1159
Block Write Access (Burst Mode)
1160
Block Read Access (Non-Burst Mode)
1161
Error Handling
1162
Examples
1163
IEEE‚ 1149.1 (JTAG) RD/WR Sequences
1164
JTAG Sequence for Read Access of Memory-Mapped Resources
1165
Nexus Crossbar Edma Interface (NXDM)
1166
Features
1167
NXDM Nexus Register Map
1168
Development Control Registers (DC1 and DC2)
1169
Watchpoint Trigger Register (WT)
1171
Data Trace Start Address Registers 1 and 2 (DTSA1 and DTSA2)
1172
Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)
1173
Breakpoint / Watchpoint Control Register 2 (BWC2)
1174
Breakpoint/Watchpoint Address Registers 1 and 2 (BWA1 and BWA2)
1175
NXDM JTAG DID Register
1176
Functional Description
1177
Tcodes Supported by NXDM
1178
Data Trace
1180
Data Trace Synchronization Messages
1181
DTM Operation
1182
DTM Queueing
1183
Watchpoint Messaging
1184
Appendix A
1186
A.1 Base Addresses of the Device Modules
1186
A.2 MPC5566 Register Map
1187
Appendix B
1252
B.1 Overview
1252
B.2 Calibration Bus
1254
B.3 Device-Specific Information
1255
B.4.3 Clkout
1256
B.8 Application Information
1257
Appendix C
1258
C.1 Changes between Revisions 1 and 2
1258
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NXP Semiconductors MPC5566 Specifications
General
Brand
NXP Semiconductors
Model
MPC5566
Category
Microcontrollers
Language
English
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