RL78 Family VDE Certified IEC60730/60335 Self Test Library
R01AN0749EG0201 Rev.2.01 Page 44 of 50
Mar 04, 2014
6.1.2 RAM Guard Protection
This is a write protection feature that when enabled allows data to be read from the selected Ram area, but
prohibits a write to these locations. No error is generated if a write occurs to this area
The Ram area available for this feature is limited and can be selected by the “GRAM0, GRAM1” bits as
shown in figure 22 below:
Figure 22 RAM Guard Protection
6.1.3 Invalid Memory Access Protection
This is a feature that provides additional protection for detection of an invalid memory access.
Please note that once the “IAWEN” bit is set in the “IAWCTL” register, it cannot be disabled except for a
Reset. Also if the Watchdog is enabled in the Flash memory Option Bytes registers, then the invalid memory
protection automatically enabled.
If an invalid memory access is detected, then an internal Reset is generated. The Reset source can be
determined by examining the “RESF” register. The “IAWRF” bit will be set if the invalid memory access
was the source of the Reset.
Figure 23 Invalid Memory Access Protection