Renesas RL78 Series Application Note

RL78 Family VDE Certified IEC60730/60335 Self Test Library
R01AN0749EG0201 Rev.2.01 Page 5 of 50
Mar 04, 2014
2. Self Test Library Functions
2.1 CPU Register Tests
This section describes CPU register tests routines. The test harness control file ‘main.c’ provides examples of the API
for each of the CPU register tests using “C” language.
These modules test the fundamental aspects of the CPU operation. Each of the API functions has a return value in order
to indicate the result of a test.
Each of the test modules saves the original contents of the register(s) under test and restores the contents on completion.
The following CPU registers are tested:
• Working registers and Accumulator: AX, HL, DE, BC in Register Banks 0 – 3
Figure 2 Working Register Configuration
• Stack Pointer (SP)
Figure 3 Stack Pointer Configuration
• Processor Status Word (PSW)
Figure 4 PSW Register Configuration

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit