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Xilinx Virtex-5 FPGA ML561 User Manual
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R
Vir
te
x-5 FPGA ML561
Memor
y Interfaces
De
velopment Boar
d
User Guide
UG199 (v1.2.1
) June 15
, 2009
2
Table of Contents
Default Chapter
2
Revision History
2
Table of Contents
3
Preface: about this Guide
7
Guide Contents
7
Additional Documentation
7
Additional Support Resources
8
Conventions
9
Typographical
9
Online Document
9
Terminology
9
Chapter 1: Introduction
11
About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit
11
Virtex-5 FPGA ML561 Memory Interfaces Development Board
12
Chapter 2: Getting Started
15
Documentation and Reference Design CD
15
Initial Board Check before Applying Power
15
Applying Power to the Board
16
Chapter 3: Hardware Description
17
Hardware Overview
17
Fpga
18
Memories
19
DDR400 SDRAM Components
19
Ddr2 DIMM
19
DDR2 SDRAM Components
20
Qdrii Sram
20
RLDRAM II Devices
20
Memory Details
21
DDR400 and DDR2 Component Memories
21
Ddr2 Sdram DIMM
23
QDRII and RLDRAM II Memories
25
External Interfaces
27
Usb
27
Rs-232
27
Clocks
27
200 Mhz LVPECL Clock
28
SMA Clock
28
33 Mhz Clock
28
33 Mhz System ACE Controller Oscillator
29
GTP Clocks
29
User I/Os
29
General-Purpose Headers
29
DIP Switch
29
Seven-Segment Displays
30
Light Emitting Diodes (Leds)
30
Pushbuttons
30
Power on or off Slide Switch
31
Soft Touch Probe Points
31
Power Measurement Header
31
Liquid Crystal Display Connector
32
Power Regulation
33
Power Distribution
33
Voltage Regulators
34
Board Design Considerations
36
Chapter 4: Electrical Requirements
39
Power Consumption
39
FPGA Internal Power Budget
46
Chapter 5: Signal Integrity Recommendations
47
Termination and Transmission Line Summaries
47
Chapter 6 : Configuration
51
Configuration Modes
51
JTAG Chain
52
JTAG Port
52
Parallel IV Cable Port
52
System ACE Interface
52
Chapter 7: ML561 Hardware-Simulation Correlation
55
Introduction
55
Test Setup
56
Signal Integrity Correlation Results
58
DDR2 Component Write Operation
59
DDR2 Component Read Operation
65
DDR2 DIMM Write Operation
70
DDR2 DIMM Read Operation
76
QDRII Write Operation
81
QDRII Read Operation
86
Summary and Recommendations
91
How to Generate a User-Specific FPGA IBIS Model
93
Appendix A: FPGA Pinouts
95
FPGA #1 Pinout
95
FPGA #2 Pinout
100
FPGA #3 Pinout
108
Appendix B: Bill of Materials
115
Appendix C: LCD Interface
119
General
119
Display Hardware Design
119
Hardware Schematic Diagram
120
Peripheral Device KS0713
121
Controller - Operation
123
Controller - LCD Panel Connections
125
Controller - Power Supply Circuits
126
Operation Example of the 64128EFCBC-3LP
127
Instruction Set
130
Read/Write Characteristics (6800 Mode)
133
Design Examples
134
LCD Panel Used in Full Graphics Mode
134
LCD Panel Used in Character Mode
135
Array Connector Numbering
139
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Xilinx Virtex-5 FPGA ML561 Specifications
General
Brand
Xilinx
Model
Virtex-5 FPGA ML561
Category
Motherboard
Language
English
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