Xilinx Zynq-7000 Manual

Chapter 32: Device Security
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Zynq-7000 EPP Technical Reference Manual www.xilinx.com 8
UG585 (DRAFT) February 15, 2012
The PS DAP controller can be permanently bypassed using the “JTAG CHAIN DISABLE” eFuse. The JTAG access
to the PL can be disabled by setting the DISABLE_JTAG configuration option when creating the PL bitstream see
UG628, Command Line Tools User Guide for more information.
33.4.6 Readback
Whenever an encrypted bitstream is loaded into the PL, readback of the internal configuration memory cannot be
performed by any of the external interfaces, including JTAG. The only readback access to the configuration memory
after an encrypted bitstream load is via PCAP-ICAP or ICAP. The PCAP-ICAP and ICAP interfaces are “trusted”
channels since access to these interfaces are from an authenticated PS image or an authenticated PL bitstream.
33.5 Source Documents

Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V