7FT-277R Technical Supplement
Circuit Description
Receive Signal Path
Incoming RF signal is from the antenna jack is delivered
to the Main Unit and passed through the low-pass filter
network, antenna switching diode D1003 and D1004
(both RLS135), and low-pass filter network to the RF
amplifier Q1022 (3SK296ZQ). The amplified RF signal is
passed through band-pass filtered again by varactor-
tuned band-pass filter consisting of coils L1024, L1025,
and L1026, and diodes D1017, D1018, and D1019 (all
HVC350B), then applied to the 1st mixer Q1023
(3SK296ZQ) along with the first local signal from the PLL
circuit.
The first local signal is generated between 382.75 MHz
and 402.75 MHz by the VCO, which consists of Q1014
(2SC5006) and varactor diodes D1009 (HVC350B), D1010
(HVC375B) and D1011 (HSC277) according to the receiv-
ing frequency.
IF and Audio Circuits
The 47.25 MHz first IF signal is applied to the monolithic
crystal filter XF1001 which strip away unwanted mixer
products, and the IF signal is applied to the first IF ampli-
fier Q1024 (2SC4915). The amplified first IF signal is then
delivered to the FM IF subsystem IC Q1004 (NJM2591V),
which contains the second mixer, limiter amplifier, noise
amplifier, and FM detector.
The 46.8 MHz second local signal which is made from
quadrupled 11.7 MHz crystal X1002 produces the 450 kHz
second IF signal when mixed with first IF signal within
Q1004 (NJM2591V).
The 450 kHz second IF signal is applied to the ceramic
filter CF1002 which strip away unwanted mixer prod-
ucts to the ceramic discriminator CD1001 which removes
any amplitude variations in the 450 kHz IF signal before
detection of speech.
The detected audio from the Q1004 (NJM2591V) is ap-
plied to a band-pass filter consisting of Q1081 and Q1082
(both 2SC4617), then passes through the audio mute gate
Q1052 (2SC4617) and Q1045 (DTC144EE).
The audio signal is passed through the audio VR which
adjusts the audio sensitivity to compensate for audio level
variations, then delivered to the audio amplifier Q1008
(TDA2822D).
Squelch Control
When no carrier received, noise at the output of the de-
tector stage in Q1004 (NJM2591V) is applied to pin 49 of
main CPU Q1001 (HD64F2266TF13), which compares the
squelch threshold level to that which set by the SQL knob.
While no carrier is received, pin 71 of Q1001
(HD64F2266TF13) remains “low,” to disable audio out-
put from the speaker.
Transmit Signal Path
The speech signal from the microphone is amplified by
Q1074 (LM2902PWR). The amplified speech signal is sub-
jected to the low-pass filter network Q1074 (LM2902PWR)
and deviation controller Q1075 (DTC144EE).
UHF Transmit Signal Path
The adjusted speech signal from Q1075 (DTC144EE) is
delivered to VCO Q1014 (2SC5006) which frequency
modulates the transmitting VCO made up of D1010
(HVC375B).
The modulated transmit signal passes through buffer
amplifier Q1013 and Q1012 (both 2SC5006).
The transmit signal applied to the Pre-Drive amplifier
Q1011 (2SC5006) and Drive amplifier Q1010 (2SK2596),
then finally amplified by Power amplifier Q1009
(2SK3476) up to 5 Watts. This two stages (Q1010 and
Q1009) power amplifier’s gain is controlled by the APC
circuit.
The 5 Watts RF signal passes through low-pass filter net-
work, antenna switch D1003 (RLS135), and another low-
pass filter network, and then deliver to the ANT jack.
TX APC Circuit
A portion of the Power amplifier output is rectified by
D1002 and D1052 (both RB751S), then delivered to APC
Q1019 (LM2904PWR), Q1020 and Q1021 (both
DTC144EE), as a DC voltage which is proportional to the
output level of the power amplifier.
The APC Q1019 (LM2904PWR) is compared the rectified
DC voltage from the power amplifier and the reference
voltage from the main CPU Q1001 (HD64F2266TF13), to
produce a control voltage, which regulates supply volt-
age to the Drive amplifier Q1010 (2SK2596) and Power
amplifier Q1009 (2SK3476), so as to maintain stable out-
put power under varying antenna loading condition.
PLL
A portion of the output from the VCO Q1014 (2SC5006),
passes through the buffer amplifier Q1017 (2SC5006), then
delivered to the programmable divider section of the PLL
IC Q1003 (MB15A01PFV1), which divided according to the
frequency dividing data that is associated with the setting
frequency input from the main CPU Q1001
(HD64F2266TF13). It is then sent to the phase comparator.
The 11.7 MHz frequency of the reference oscillator circuit
made up of X1002 is divided by the reference frequency
divider section of Q1003 (MB15A01PFV1) into 2340 or
To Next Page
Loading...
Need help?
General
