ARM Cortex-M3 DesignStart User Manual

3.15 Audio configuration
The FPGA design implements a simple serial interface that is based on I
2
C.
The following table describes the registers for the audio I
2
C control interface:
Table 3-3 I
2
C control interface registers
Address Name Description
0x40023000
CONTROL Reads from this register return:
1 Serial Data (SDA) input
0 Serial Clock (SCL) output
0x40023000
SET[1:0] Bits written as 0b1 set the appropriate
output bit:
1 SDOUTEN_n
0 SCL
0x40023004
CLEAR[1:0] Bits written as 0b1 clear the appropriate
output bit:
1 SDOUTEN_n
0 SCL
Reads from this register return 0b00.
The serial data is driven LOW when SDOUTEN_n is driven high, otherwise it is configured as an input
pin.
The audio I
2
C control interface drives the Cirrus Logic CS42L52 codec chip on the baseboard.
3 FPGA platform overview
3.15 Audio configuration
ARM 100896_0000_00_en Copyright © 2017 ARM Limited or its affiliates. All rights reserved. 3-40
Non-Confidential

ARM Cortex-M3 DesignStart Specifications

General

Brand	ARM
Model	Cortex-M3 DesignStart
Category	Motherboard
Language	English

Summary

Preface

About this book

This book describes how to use the FPGA platform in the ARM Versatile™ Express Cortex®-M Prototyping System to evaluate a design developed using Cortex-M3 DesignStart™ Eval.

Document Conventions

Details typographic conventions, timing diagram components, and signal conventions used in the document.

Providing Feedback

Instructions for providing feedback on the product and document content to ARM.

Chapter 1 Introduction

1.1 About Cortex®-M3 DesignStart™ Eval

Introduces Cortex-M3 DesignStart Eval, its purpose, package contents, and ecosystem.

1.2 ARM Versatile Express Prototyping System

Describes the MPS2+ platform, its features, and its role in the Cortex-M3 ecosystem.

1.3 Using the Documentation

Lists and describes related documents for the Cortex-M3 DesignStart Eval, including purpose and scope.

1.4 FPGA Evaluation Flow Directory Structure

Details the main directories of the Cortex-M3 DesignStart Eval FPGA Evaluation Flow.

1.5 Limitations

Describes limitations of the Cortex-M3 DesignStart Eval FPGA Evaluation Flow, including deliverables and processor support.

Chapter 2 Using the Prebuilt FPGA Image

2.1 Setting Up the MPS2+ FPGA Platform

Provides step-by-step instructions to set up the MPS2+ platform with the Cortex-M3 DesignStart Eval image.

2.2 Running the Self-Test Program

Details how to run the self-test program on the MPS2+ platform and configure the UART.

2.3 Connecting to a Debugger

Explains how to connect to the MPS2+ platform for debugging using CMSIS-DAP over USB.

Chapter 3 FPGA Platform Overview

3.1 System Overview

Provides a block diagram and description of the FPGA design's functional hierarchy and components.

3.3 Block RAM Instances

Details the implementation of 256KB block RAM as 32-bit AHB SRAM and four 32KB regions for program RAM.

3.4 External Zero Bus Turnaround SSRAM

Describes the ZBT SSRAM in the FPGA platform, including ZBT SSRAM1 and ZBT SSRAM2/3.

3.14 Audio I2S

Describes the memory map for I2S audio registers, detailing control, status, and data registers.

Chapter 4 Clocks

4.1 Source Clocks

Lists the source clocks for the FPGA design and their respective frequencies.

4.2 Derived Clocks

Details the derived clocks for the FPGA design, their frequencies, and their source.

Chapter 5 Serial Communication Controller

5.1 SCC Interface Overview

Provides an overview of the SCC interface for communication between the microcontroller and FPGA system.

5.2 SCC Memory Map

Details the SCC register memory map, including configuration, status, and ID registers.

Chapter 6 FPGA Build

6.1 Build Flow

Describes the two stages of the build flow: creating a new user bit file and loading it onto the MPS2+ platform.

6.2 Build Requirements

Specifies the Intel Quartus software version required to build the FPGA files.

Chapter 7 Integrating with mbed™ OS

7.1 Compatibility with mbed™ OS

Confirms MPS2+ platform support as a target in the mbed online compiler and provides links for more information.

Chapter 8 Performance and Utilization

8.1 Performance and Clocks

Discusses source and derived clocks in the FPGA board default system and recommends against modification.

8.2 Utilization of Default System

Shows FPGA resources and Cortex-M3 DesignStart Eval code utilization of these resources.

Appendix A Revisions

A.1 Revisions - Cortex®-M3 DesignStart™ Eval

Describes technical changes between released issues of the document.