Clevo N550RN User Manual

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FLOAT FOR SKL
GND FOR CNL
NEAR CPU
CAD Note: Capacitor need to be placed
close to buffer output pin
CFG7
DEFENSIVE PULL DOWN SITE
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG4
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
DISPLAY PORT PRESENCE STRAP
CFG2
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PCIE PORT BIFURCATION STRAPS
VCCST_PWRGD
CFG[0]: Stall reset sequence after PCU Θ
ΘΘ
Θ
PLL lock until de-asserted:
— 1 = (Default) Normal Operation;
No stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
Θ
ΘΘ
Θ
CFG[2]: PCI Express* Static x16 Lane Θ
ΘΘ
Θ
Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane.
Θ
ΘΘ
Θ
CFG[4]: eDP enable: Θ
ΘΘ
Θ
— 1 = Disabled.
— 0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation Θ
ΘΘ
Θ
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
Θ
ΘΘ
Θ
— 1 = (default) PEG Train
immediately following RESET# de
assertion.
— 0 = PEG Wait for BIOS for
training.
CFG[19:8]: Reserved configuration
Θ
ΘΘ
Θ
lanes.
NEAR CPU
H_PROCHOT#_RH_PROCHOT#
H_CATERR#
H_PM_DOWN_R
H_SKTOCC_N
CFG_RCOMP
CPU_VIDALERT_N
SKL_XDP_MBP_0
SKL_XDP_MBP_1
SKL_MBP_2
SKL_MBP_3
H_TDO
H_TDI
H_TMS
H_TCK
H_TRST#
H_PREQ#
H_PRDY#
CFG17
CFG16
CFG19
CFG18
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG11
CFG12
CFG13
CFG14
CFG15
CFG10
CFG0
VCCST_PWRGD_CPU
CFG9
H_PROCHOT#
H_TDO
H_TCK
H_PECI_R
VCCST_PWRGD
H_SKTOCC_N
H_TDI
H_TMS
VCCST_PWRGD
1.0V_VCCST
VCCIO
1.0DX_VCCSTG
1.0V_VCCST
1.0V_VCCST3.3VA
3.3VA
H_PROCHOT#45,46,48
H_PM_DOWN24
H_CPU_SVIDCLK46,48
H_CPU_SVIDDAT46,48
H_CPU_SVIDALRT#46,48
H_PECI33
DDR_VTT_PG_CTRL40
PCH_THERMTRIP#24
H_SKTOCC_N26
H_PRDY# 29
H_TDO 25
PCH_PECI24
1.0DX_VCCSTG6,42,45
VCCIO2,6,41
1.0V_VCCST6,24,41,46,48
3.3VA22,23,24,25,26,28,29,41,42
ALL_SYS_PWRGD11,23,33,46,48
PCH_CPU_BCLK_R_DN27
PCH_CPU_BCLK_R_DP27
PCH_CPU_PCIBCLK_R_DN27
PCH_CPU_PCIBCLK_R_DP27
CPU_24MHZ_R_DN27
CPU_24MHZ_R_DP27
H_PWRGD25
PLTRST_CPU_N24
H_PM_SYNC24
H_TRST# 29
H_PREQ# 29
H_PROCHOT_EC33
H_TMS 25
H_TCK 25
H_TDI 25
Title
Size Document Number Rev
Date: Sheet
of
6-71-N5500-D02A
D01
[04]Processor 3/6-CLK/MISC
A3
455W ednesday, September 09, 2015
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N550RC
Title
Size Document Number Rev
Date: Sheet
of
6-71-N5500-D02A
D01
[04]Processor 3/6-CLK/MISC
A3
455W ednesday, September 09, 2015
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N550RC
Title
Size Document Number Rev
Date: Sheet
of
6-71-N5500-D02A
D01
[04]Processor 3/6-CLK/MISC
A3
455W ednesday, September 09, 2015
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N550RC
R356 *51_04
R358 *1K_04
R359 *51_04
R70 1K_04
R368 *1K_04
R355 *51_04
C616
*0.1u_16V_Y5V_04
R65 *1K_04
R386 60.4_1%_04
R346 20_1%_04
R366 *1K_04
R62
100_04
R342 0_04
R339 *12.1_1%_04
R57
220_04
S
D
G
Q16B
MTDK3S6R
5
34
R373 *1K_04
R397
100K_04
SKYLAKE_HALO
BGA1440
5 OF 14
REV = 1
?
?
U1E
SKL_H_BGA_BGA
PROC_SELECT#
BN1
CATERR#
BM30
SKTOCC#
BR33
PM_DOWN
BP31
PM_SYNC
BM34
RESET#
BP35
PROCPWRGD
BT31
VCCST_PWRGD
H13
CFG[17]
BN23
CFG[15]
BT19
CFG[16]
BP23
CFG[11]
BT22
CFG[12]
BM19
CFG[10]
BT23
CFG[9]
BR22
CLK24N
D31
CFG[1]
BN27
CFG[3]
BN28
CFG[18]
BN22
PROC_TDI
BL32
CFG[0]
BN25
CFG[2]
BN26
CFG[4]
BR20
CFG[6]
BT20
CFG[5]
BM20
CFG[7]
BP20
CFG[8]
BR23
CFG[13]
BR19
CFG[14]
BP19
CFG[19]
BP22
PROC_PREQ#
BL30
PROC_PRDY#
BP27
VIDSCK
BH32
PROC_TDO
BT28
CLK24P
E31
PCI_BCLKN
C36
PCI_BCLKP
D35
BCLKN
A32
VIDSOUT
BH29
PROCHOT#
BR30
DDR_VTT_CNTL
BT13
CFG_RCOMP
BT25
PROC_TRST#
BP30
PROC_TCK
BR28
PROC_TMS
BP28
VIDALERT#
BH31
THERMTRIP#
J31
PECI
BT34
BCLKP
B31
BPM#[0]
BR27
BPM#[1]
BT27
BPM#[2]
BM31
BPM#[3]
BT30
R377 *1K_04
R357 *1K_04
R372 *1K_04
R351 499_1%_04
R379 *1K_04
R74 *1K_04
R388
1K_04
R367 *1K_04
R369 *1K_04
R380 1K_04
R378 *1K_04
R352 1K_04
R66 *1K_04
R343 100K_04
R56
56.2_1%_04
R409 *0_04
R64 *51_04
R364
49.9_1%_04
R408
*100K_04
S
D
G
Q16A
MTDK3S6R
2
61
Q20
2SK3018S3
G
DS
R381 *1K_04
C585
47p_50V_NPO_04
Sheet 4 of 72
Processor 3/6
Schematic Diagrams
Processor 3/6 B - 5
B.Schematic Diagrams
Processor 3/6

Clevo N550RN Specifications

General

Brand	Clevo
Model	N550RN
Category	Laptop
Language	English