37
DVD-2910/955
TSD0
33
O Audio transmit serial data port 0.
SEL_PLL0 I Refer to the description and matrix for SEL_PLL2 pin 32.
TSD1
36
O Audio transmit serial data port 1.
SEL_PLL1 I Refer to the description and matrix for SEL_PLL2 pin 32.
TSD2 37 O Audio transmit serial data output 2.
TSD3 38 O Audio transmit serial data output 3.
NC 48 — No connect pins. Leave open.
MCLK 39 I/O Audio master clock for audio DAC.
TBCK 40 O Audio transmit bit clock.
SEL_PLL3
41
I Clock source select. Strapped to VCC or ground via 4.7-kΩ resistor; read only
during reset.
SPDIF_OUT O S/PDIF output.
SPDIF_IN 42 I S/PDIF input.
RSD 45 I Audio receive serial data.
RWS 46 I Audio receive frame sync.
RBCK 47 I Audio receive bit clock.
XIN 49 I 27-MHz crystal input.
XOUT 50 O 27-MHz crystal output.
AVEE 51 P Analog power for PLL.
AVSS 52 G Analog ground for PLL.
DMA[11:0] 53:58, 61:66 O DRAM address bus.
DCAS# 69 O DRAM column address strobe.
DOE#
70
O DRAM output enable (active-low).
DSCK_EN O DRAM clock enable.
DWE# 71 O DRAM write enable (active-low).
DRAS# 72 O DRAM row address strobe (active-low).
DMBS0 73 O DRAM bank select 0.
DMBS1 74 O DRAM bank select 1.
DB[15:0] 77:82, 85:90, 93:96 I/O DRAM data bus.
DCS[1:0]# 97,100 O DRAM chip select (active-low).
DQM 101 O Data input/output mask.
ES6138F Pin Description (Continued)
Name Pin Numbers I/O Definition
SEL_PLL3 Clock Source
0 Crystal oscillator
1 DCLK input
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
To Next Page
Loading...
Need help?
General
