37
Using BIOS
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
LDT & PCI Bus Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
LDT Configuration (Enabled)
This item enables or disables the LDT configuration.
Upstream LDT Bus Width (16 bit)
This item allows users to manually adjust the upstream LDT bus width to be 8 bit or
16 bit.
Downstream LDT Bus Width (16 bit)
This item allows users to manually adjust the downstream LDT bus width to be 8 bit
or 16 bit.
LDT Bus Frequency (Auto)
This item allows users to manually adjust the LDT Bus Frequency.
PCIE Reset Delay (Disabled)
This item enables or disables the PCIE reset delay.
Press <Esc> to return to the Advanced Chipset Features page.
LDT Configuration [Enabled]
Upstream LDT Bus Width [16 bit]
Downstream LDT Bus Width [16 bit]
LDT Bus Frequency [Auto]
PCIE Reset Delay [Disabled]
Item Help
Menu Level
Phoenix-Award WorkstationBIOS CMOS Setup Utility
LDT &PCI Bus Control
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
PCIE GFX Core Payload Size (64 Bytes)
This item allows users to manually adjust the PCIE GFX Core Payload size.
PCIE GPP Core Payload Size (64 Bytes)
This item allows users to manually adjust the PCIE GPP Core Payload size.
GFX0 Link Width (x16)
This item allows users to manually set the GFX Link Width.
UMA Frame Buffer Size (256 MB)
This item allows users to manually adjust the UMA frame buffer size, from 16 MB to
256 MB.
Current UMA Size (256 MB)
This item shows the current UMA Frame Buffer Size.
To Next Page
Loading...
Need help?
General
