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5. CIRCUIT DESCRIPTION
5-1 MICRO CONTROLLER CIRCUIT
MICRO Controller
The IC101 contains a 6502/8051 8-bit CPU core, 512 bytes of RAM, 16K bytes of ROM,14 channel 8
bit PWM D/A converters, 2 channel A/D converters for key detection, one 8 bit pre-loadable base
timer, internal H-sync and V-sync signals processor providing mode detection, watch- dog timer
preventing system from abnormal operation, and an I²C bus interface.
H/V sync signals processor
The functions of the sync processor include polarity detection, H-SYNC & V-SYNC signals counting,
Programmable SYNC signals output, free running signal generator. Pin39/Pin40 are for the H-SYNC
and V-SYNC input, Pin32/Pin33 will output the same signal as input sync signal without delay, and the
polarity are setting in the positive. When no signal input, the Pin32 will output a 72Hz V-SYNC free run
signal. The Pin33 will output a 48KHz H-SYNC free run signal. for the monitor testing use.
5-2 DEFLECTION CIRCUIT
The deflection circuit is achieved by a high performance and efficient solution IC 401 (STV9118) for
this monitor. The concept is fully DC controllable and can be used in applications with a micro-
controller solutions.
The STV9118 provides sync. Processing with full auto sync. Capability, a flexible SMPS block and an
extensive set of geometry control facilities. Further the IC generates the drive waveforms for DC
coupled vertical boosters to the STV9302A.
Horizontal Oscillator
The oscillator is of the relaxation type and requires a capacitor of C409 at pin6. The free running
frequency is determined by a resistor R412 from pin8 to ground.
PLL 1 Phase Detector
The phase detector is a standard one using switched current sources. It compares the middle of H-
sync. with a fixed point on the oscillator saw-tooth voltage. The PLL loop filter C435, C437, R411 is
connected to Pin9.
PLL2 Phase Detector
This phase detector is similar to the PLL1 detector and compares the line flyback pulse at pin 12 with
the oscillator saw-tooth voltage. The PLL2 detector thus compensates for the delay in the external H-
deflection circuit by adjusting the phase of the HDRV output pulses. The phase between H-flyback and
H-sync can be controlled at pin5.
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