MMDSP Debugger 1 6
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Daisy-chain Example
Below, configuration for core C.
Instruction register length of
• Core A: 3 bit
• Core B: 5 bit
• Core D: 6 bit
SYStem.CONFIG.IRPRE 6 ; IR Core D
SYStem.CONFIG.IRPOST 8 ; IR Core A + B
SYStem.CONFIG.DRPRE 1 ; DR Core D
SYStem.CONFIG.DRPOST 2 ; DR Core A + B
SYStem.CONFIG.CORE 0. 1. ; Target Core C is Core 0 in Chip 1
Core A Core B Core C Core D TDOTDI
Chip 0 Chip 1