Computer Hardware

Spectra 70

RCA Spectra 70 Training Manual

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OP

Ll

L2

Bl

Dl

B2

D2

GENERATED

I

FG

16

2

I

3

I

110 I

4002

10

I 2

10

0024

10

I

INSTRUCTION

*

General

Register

one

contains

0000

General

Register

two

contains

4096

10

CONDITION CODE = 0 (OPERANDS EQUAL)*

Note

that

because

the

second

operand

was

longer

than

the

first

operand

the

Condition

Code

does

not

reflect

the

true

relative

value

of

each

field.

Had

the

operands

been

reversed,

i.

e.,

BAL

(4),

C

HK

(3),

the

Condition

Code

would

have

been

set

to

2

(first

operand

high).

BRANCH

ON

CONDITION INSTRUCTION

The

Branch

On

Condition

(BC)

instruction

transfers

control

based

on

the

setting

of

the

Condition

Code

indicator.

The

BC

is

a

four-byte

instruction

with

the

second

byte

being

a

mask

specifying

in

the

four

high-order

bits

the

Condition

Code

setting(s)

upon

which

the

transfer

of

control

depends.

A 1

bit

in

the

respective

bit

pOSitions below

generates

a

transfer

of

control

if

the

Condition

Code

Indicator

is

set

to

the

position

shown.

24

Condition

Code 3

2

5

Condition

Code

2

2

6

Condition

Code 1

27

Condition

Code 0

The

least

significant

four

bits

of

the

mask

(2

0

to

2

3

)

must

be

zero.

In

assembly

language,

however,

the

mask

is

speci-

fied

as

one

hexadecimal

digit

and

the

four

least-

significant

zero

bits

will

be

generated.

Example:

In

the

following

example,

assume

thatthe

BC

instruc-

tion

follows

a

decimal

subtract

instruction

and

the

programmer

wants

to

transfer

control

to

an

error

routine

(ERRT)

if

overflow

has

occurred

or

to

an

overdraft

(OVDF)

routine

if

the

result

of

the

sub-

traction

is

negative.

For

a

positive

or

zero

result,

he

enters

a

process

(PRCS)

routine.

The

coding

would be:

NAME

OPERATION

OPERAND

SP

I

BAL

(4).

AMT

(3)

SUBTR.

AMT.

FROM

BAL.

I

CC3

Be

X'I'.

ERRT

BR.

TO

ERROR

RTN

eel

Be

X'4'.

OVDF

BR.

TO

OVERDR.

RTN

PRes

ENTER

PRoe.

RTN.

38

An

unconditional

transfer

of

control

takes

place

if

all

the

high-order

bits

have

a

value

of

1.

The

Branch

(B)

operation

code

Simplifies

the

writing

of

this

instruction.

A

mask

of

X'FO'

(11110000

2

)

is

generated

automatically.

Thus,

each

of

the

following

generates

an

unconditional

transfer

to

STRT.

OPERATION OPERAND

BC

X'F',

STRT

OPERATION OPERAND

B

STRT

BRANCH

AND

LINK INSTRUCTION

This

instruction

performs

an

unconditional

branch

and

stores

a

return

address

in

a

specified

register.

It

is

a

four-byte

instruction

with

the

four

high-order

bits

of

the

second

byte

specifying

a

general

register

used

for

storage

of

the

P

Register.

(The

P

Register

after

staticizing,

contains

the

address

of

the

next

in-

struction.)

The

P

Register

address

is

stored

before

branching

takes

place.

The

register

that

stores

the

P

Register

may

be

used

for

return

linkage

as

in

the

example

shown

below.

Example:

In

the

following

example,

a BRANCH

AND

LINK

in-

struction

transfers

control

to

a

routine

at

location

EDIT.

NAME

OPERATION

OPERAND

l

f

~

TRFED

BAL

10,

EDIT

RETRN

The

P

Register

(containing

the

address

of RETRN)

is

stored

in

General

Register

10.

At

the

conclusion

of

the

edit

routine,

the

same

register

may

be

used

for

return

as

follows:

NAME

OPERATION

OPERAND

EDIT

!

f

BC

X'F',

0(10)

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RCA Spectra 70 Specifications

General

Brand	RCA
Model	Spectra 70
Category	Computer Hardware
Language	English

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