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Clevo NP71PNP User Manual

Clevo NP71PNP
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A
A
VCCST_OVERRIDE
1.05v to 3.3v LEVEL SHIFT
BUF_PLT_RST#
TO VR_ON & EC
CLOCK GENERATOR
DESIGN NOTE:
㚫㚱 ⸚㒦 ⓷柴婳㉱ GND⊭央
VIA㗪␐ 婳怈 20mil
SM BUS
XTAL 25MHz 20ppm CL<=12pF
6-22-25R00-1B6
㸸柕㚱
PD
INPUT
⎗䓐
1.8V
2021/10/25
Rubband
2021/11/9
Rubband
VDD3
3.3VA3.3VA
VDD3
3.3VS
VDD3
VDD3
VDD3
3.3VS
3.3VA
5VS
3.3VS
VDD3
VDD3
VCC_RTC
VDD3
VDD3
VIN
VDD3
VDD3
VDD3
RTC_VBAT
VDD3
VDD3
VDD3
VCCST_OVERRIDE9,10
PLT_RST#9,33
BUF_PLT_RST# 41,44,45,47,48,50
SUSB#9,35,39,49,53,56,67,72
DDR 1.35V_PWRGD56
ALL_SYS_PWRGD 9,36,51,57
RSMRST#9,39
H_VR_READY57
PM_PCH_PWROK 9,39
GCLK_32K 6
PM_PCH_PWROK9,39
SMB_DATA_MAIN_DDR4 13,14
SMB_CLK_MAIN_DDR4 13,14
SMB_CLK 7,56
SMB_DATA 7,56
RSMRST#9,39EC_RSMRST#51
NV_EN_DOWN33
SLP_SUS# 9,40,44,51
SUSBC_EC#51
SUSB# 9,35,39,49,53,56,67,72
SUSC# 56
SUSC#_PCH9,51
SUSB#_PCH9,51
VCCIN_AUX_VID011,61
VCCIN_AUX_VID111,61
VCCST_EN 54
VCC1P8_CPU_EN 54
SLP_S0#9,51
Title
Size Document Number Rev
Date: Sheet
of
6-71-NP5P0-D02
D02
[39] PM CONTROL,CLK GEN
A3
39 72Wednesday, December 29, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
ADL-H+GN20-E3
Title
Size Document Number Rev
Date: Sheet
of
6-71-NP5P0-D02
D02
[39] PM CONTROL,CLK GEN
A3
39 72Wednesday, December 29, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
ADL-H+GN20-E3
Title
Size Document Number Rev
Date: Sheet
of
6-71-NP5P0-D02
D02
[39] PM CONTROL,CLK GEN
A3
39 72Wednesday, December 29, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
ADL-H+GN20-E3
R510 0_04PCH
T73
D18
ZD5231BS2
PCH
AC
T70
C648 0.1u_6.3V_X5R_02
R276 1K_04
PCH
R284 *0_04PCH
R829
100K_1%_04
PCH
C701
*0.1u_10V_X7R_04
PCH
U12
U74AHCT1G32
1.8V
4
53
1
2
U29
74AHC1G08GW PCH
1
2
5
4
3
S
D
G
Q6A
MTDK3S6R
PCH
2
61
R828
100K_1%_04
PCH
R261 *0_04PCH
C636 *0.1u_6.3V_X5R_02
R502
100K_04
PCH
R260
1K_04
PCH
Q19
SM3018KWH
PCH
G
DS
R344 *0_04
R831 1K_04PCH
C628 0.1u_6.3V_X5R_02
R287 1K_04
PCH
R491 100K_04PCH
C729 *0.1u_10V_X7R_04PCH
R383 0_04
U36
74AHC1G08GW
CPU
1
2
5
4
3
R486
100K_04
PCH
R562
*100K_04
CPU
Q44
SM3018KWH
CPU
G
DS
R838
100K_04
PCH
S
D
G
Q7A
MTDK3S6R
PCH
2
61
R470
10K_04
PCH
C639 12p_50V_NPO_04
X2
19001-X-016-3
2 1
3 4
U28A
74LVC08APW
PCH
1
2
3
147
PQ13
MMBT3904H
CPU
B
E C
R335 0_04
C629 12p_50V_NPO_04
C539 *1u_6.3V_X5R_02
PCH
U35
74AHC1G08GW
CPU
1
2
5
4
3
R563 0_04
Q14
MMBT3904H
PCH
B
E C
U14
U74AHCT1G32
1.8V
4
53
1
2
C652 2.2u_6.3V_X5R_04
R277
1K_04
PCH
R452 1K_04PCH
R471 0_04
PCH
R469
100K_04
PCH
R434
*100K_04
PCH
U37
74AHC1G08GW
CPU
1
2
5
4
3
S
D
G
Q6B
MTDK3S6R
PCH
5
34
C654 22u_6.3V_X5R_06
R488
100K_1%_04
PCH
R506 *0_04PCH
C543 *1u_6.3V_X5R_02
PCH
U11
U74AHCT1G32
1.8V
4
53
1
2
R381 330_04
U28C
74LVC08APW
PCH
9
10
8
147
C712
*0.1u_6.3V_X5R_02
PCH
R500
100K_04
PCH
R487 0_04PCH
U28D
74LVC08APW
PCH
12
13
11
147
R489 430K_04PCH
U17
SLG3NB3426VTR
PCB Footprint = TQFN16_2X3MM-GCLK
X2-OUT
16
NC
11
VIOE_19.2M
8
GND
5
19.2M
6
25M
4
GND
7
32.768K
9
VRTC
10
VIO_25M
3
GND
13
VOUT
14
X1-IN
1
PAD
17
VDD
2
V3.3A
15
NC
12
S
D
G
Q7B
MTDK3S6R
PCH
5
34
R369 0_04
U28B
74LVC08APW PCH
4
5
6
147
R352 0_04
3.3_VCCST_OVERRIDE
3.3_VCCST_OVERRIDE
SUSB#
SUSB#
S0&S4_PWRGD
ALL_SYS_PWRGD_R ALL_SYS_PWRGD
ALL_SYS_PWRGD
RSMRST#
SUSB#_PCH
SUSC#_PCH
SUSBC_EC#
VCCIN_AUX_VID_0_1
VCCIN_AUX_VID_0_1
SUSB#
Sheet 38 of 69
PM Control, Clock
Gen
Schematic Diagrams
PM Control, Clock Gen B - 39
B.Schematic Diagrams
PM Control, Clock Gen

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Clevo NP71PNP Specifications

General IconGeneral
BrandClevo
ModelNP71PNP
CategoryLaptop
LanguageEnglish

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