19
AVR-1907 / AVR-787 / AVC-1630
BU2090F (IC1005,1008)
MM74LCX244 (IC809-811)
Function
Pin
No.
Pin Name I/O
* For latch-up countermeasure, perform each power supply ON/OFF in the same timing.
28 XOUT O X’tal osc. connecting output terminal
29 XIN I X’tal osc. connection, external clock input terminal (24.576MHz or 12.288MHz)
30 DVDD — Digital power
31 DGND — Digital GND
32 EMPHA/UO I/O Emphasis information/U-data output/Chip address setting terminal
33 AUDIO/VO I/O Non-PCM detect/V-flag output/ Chip address setting terminal
34 CKST I/O Clock switch transition period output/Demodulation master or slave function switching terminal
35 INT I/O Interrupt output for
μ
μ
μ
μ
μ
com (Interrupt factor selectable)/Modulation or general I/O switching terminal
36 RERR O PLL lock error, data error flag output
37 DO O com I/F, read out data output terminal (3-state)
38 DI I com I/F, write data input terminal
39 CE I com I/F, chip enable input terminal
40 CL I com I/F, clock input terminal
41 XMODE I System reset input terminal
42 DGND — Digital GND
43 DVDD — Digital power
44 TMCK/PIO0 I/O 256fs system clock input for modulation/General I/O in/output terminal
45 TBCK/PIO1 I/O 64fs bit clock input for modulation/General I/O in/output terminal
46 TLRCK/PIO2 I/O fs clock input for modulation/General I/O in/output terminal
47 TDATA/PIO3 I/O Serial audio data input for modulation/General I/O in/output terminal
48 TXO/PIOEN O/I Modulation data output/ General I/O enable input terminal
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11Q3
VDD
OE
Q7
Q8
Q11
Q10
Q9
Q6
VSS
DATA
CLOCK
LCK
Q0
Q1
Q2
9
10
Q4
Q5
CONTROL CIRCUIT
12-bit SHIFT REGISTER
12-bi
t
STRAGE REG
I
STER
OUTPUT BU FFER
(OPE
NDRA
I
N)
1
2
3
4
5
6
7
8
20
19
18
16
15
14
13
I3
VCC
OE2
O2
I5
O0
I4
O1
I6
OE
I0
O4
I1
O5
I2
O6
912
O7 O3
10 11
GND
I7
17
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
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