184
SA7121PinDescription
1997 Jan 06 4
Philips Semiconductors Preliminary specification
Digital Video Encoder (ConDENC) SAA7120; SAA7121
PINNING
SYMBOL PIN I/O DESCRIPTION
res. 1 − reserved
SP 2 I test pin; connected to digital ground for normal operation
AP 3 I test pin; connected to digital ground for normal operation
LLC 4 I line-locked clock; this is the 27 MHz master clock for the encoder
V
SSD1
5 I digital ground 1
V
DDD1
6 I digital supply voltage 1
RCV1 7 I/O raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal
RCV2 8 I/O raster control 2 for video port; this pin provides an HS pulse of programmable length or
receives an HS pulse
MP7 9 I
MPEG port; it is an input for
“CCIR 656”
style multiplexed Cb Y, Cr data
MP6 10 I
MP5 11 I
MP4 12 I
MP3 13 I
MP2 14 I
MP1 15 I
MP0 16 I
V
DDD2
17 I digital supply voltage 2
V
SSD2
18 I digital ground 2
RTCI 19 I Real Time Control input; if the LLC clock is provided by an SAA7111 or SAA7151B,
RTCI should be connected to pin RTCO of the decoder to improve the signal quality
res. 20 − reserved
SA 21 I the I
2
C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH
res. 22 − reserved
res. 23 − reserved
C 24 O analog output of the chrominance signal
V
DDA1
25 I analog supply voltage 1 for the C DAC
res. 26 − reserved
Y 27 O analog output of VBS signal
V
DDA2
28 I analog supply voltage 2 for the Y DAC
res. 29 − reserved
CVBS 30 O analog output of the CVBS signal
V
DDA3
31 I analog supply voltage 3 for the CVBS DAC
V
SSA1
32 I analog ground 1 for the DACs
V
SSA2
33 I analog ground 2 for the oscillator and reference voltage
XTALO 34 O crystal oscillator output (to crystal)
XTALI 35 I crystal oscillator input (from crystal); if the oscillator is not used, this pin should be
connected to ground
V
DDA4
36 I analog supply voltage 4 for the oscillator and reference voltage
XCLK 37 O clock output of the crystal oscillator
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