EasyManuals Logo
Home>Intel>Motherboard>945GC

Intel 945GC User Manual

Intel 945GC
52 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #38 background imageLoading...
Page #38 background image
34
3-6 Advanced Chipset Features
The Advanced Chipset Features Setup option is used to change the values of the chipset
registers. These registers control most of the system options in the computer.
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Timing Selectable By SPD
* DRAM CAS Latency Time Auto
* DRAM RAS# to CAS# Delay Auto
* DRAM RAS# Precharge Time Auto
* DRAM Cycle Time Auto
* DRAM Write Recovery Time Auto
* DRAM Min Ref toAct/CMD Time Auto
* DRAM Int Wrt to Rd Delay Auto
* DRAM Row Act to Row Act Delay Auto
* DRAM Int Rd to Pre Delay Auto
System BIOS Cacheable Disabled
Memory Hole at 15-16M Disabled
PCI Press Root Port Function Press enter
Menu Level >
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
DRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: Auto, 3, 4 and 5.
DRAM RAS-to-CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in
the system.
DRAM Ras Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
3-7 Integrated Peripherals
Phoenix – AwardBIOS CMOS Setup Utility
Integrated Peripherals
Item Help
> Onboard IDE Function Press Enter
> Onboard Device Function Press Enter
> Onboard Super IO Function Press Enter
PWR status after PWR Failure Always Off
Init Display First PCI Slot
Menu Level >
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
Onboard IDE Function

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel 945GC and is the answer not in the manual?

Intel 945GC Specifications

General IconGeneral
BrandIntel
Model945GC
CategoryMotherboard
LanguageEnglish

Related product manuals