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Intel Xeon Phi User Manual

Intel Xeon Phi
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Intel® Xeon Phi Coprocessor DEVELOPERS QUICK START GUIDE
13
Working directly with the uOS Environment Intel® Xeon Phi™ Coprocessor
Since the coprocessor is running Linux and is effectively a separate network node, root or non-root users can
log into it via sshand issue many common Linux commands. Files are transferred to/from the coprocessor
using “scp” or other means.
The default IP address for the coprocessor as seen from the host is 172.31.<coprocessor>.1, while the
coprocessor sees the host at 172.31.<coprocessor>.254 by default. The coprocessor can also be
referred to from the host by the alias mic<coprocessor>. For example, the first coprocessor you install in
your system is called “mic0 and is located at 172.31.1.1. It sees the host as 172.31.1.254. If a second
coprocessor were installed, it would be called mic1and located at 172.31.2.1, and it would see the host
as 172.31.2.254.
For detailed information on setting up the card for non-root users, adjusting the network configuration,
mounting an NFS file system exported by the host for use on the Intel® Xeon Phi coprocessor, etc., please
see the document Intel® MPSS User’s Guide.
Useful Administrative Tools
This product ships with the following administrative tools, found in the /usr/bindirectory. Root, and
users needing to use these tools, should add this directory to their default path:
micinfo - provides information about host and coprocessor system configuration.
micflash - updates the flash on the coprocessor; saves and retrieves the version and other
information for each section of the flash
micsmc - a tool designed to ease the burden of monitoring and managing Intel® Xeon Phi™
coprocessors.
miccheck a utility for verifying the configuration of an Intel® Xeon Phi™ coprocessor by running
various diagnostic tests.
micnativeloadex a utility that will copy an Intel® MIC Architecture native binary to a specified Intel®
Xeon Phi™ coprocessor r and execute it
micctrl a tool to help the system administrator configure and restart the coprocessor
micrasd an application running on the host to handle and log hardware errors.
mpssflash the POSIX version of micflash.
mpssinfo the POSIX version of micinfo.
Please see section 8 in the MPSS User’s Guide for details on these tools and their arguments.
Getting Started/Developing Intel® Xeon Phi™ Software
You develop applications for the Intel® MIC Architecture using your existing knowledge of multi-core and SIMD
programming. The offload language extensions allow you to port sections of your code (written in C/C++ or
FORTRAN) to run on the Intel® Xeon Phi™ Coprocessor, or you can port your entire application to the Intel® MIC
Architecture. Best performance will only be attained with highly parallel applications that also use SIMD
operations (generated by the compiler or using compiler intrinsics) for most of their execution.

Table of Contents

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Intel Xeon Phi Specifications

General IconGeneral
Threads per core4
ThreadsUp to 288
InterfacePCIe 3.0 x16
PCIe Version3.0
CoresUp to 72
MemoryUp to 16 GB
TDP215 W to 300 W
SocketLGA 3647
Manufacturing Process14 nm
Instruction Setx86-64
Process Technology14nm

Summary

Understanding the Intel® Xeon Phi™ Coprocessor

Introduction

Overview of the Intel® Xeon Phi™ Coprocessor and its purpose.

Intel® Many Integrated Core Architecture Overview

Details the architecture of the Intel® Xeon Phi™ Coprocessor, including its cores and vector units.

Intel® Xeon Phi™ System Setup and Installation

Preparing Your System for First Use

Guides through the initial setup and installation of drivers and software.

Steps to install the Software Development tools

Instructions for installing the necessary compilers and development tools.

Regaining Access to the Intel® Xeon Phi™ Coprocessor after Reboot

Procedures for re-establishing access to the coprocessor after a system reboot.

Developing Applications for Intel® Xeon Phi™

Getting Started/Developing Intel® Xeon Phi™ Software

Introduces the process of developing applications for the Intel® Xeon Phi™ Coprocessor.

Available Software Development Tools / Environments

Lists and describes the compilers, libraries, and tools for development.

Documentation and Sample Code

Points to essential documentation and sample code for learning and development.

Optimizing Performance on Intel® Xeon Phi™

Using the Offload Compiler – Explicit Memory Copy Model

Explains the explicit memory copy model for offloading code to the coprocessor.

Parallel Programming Options on the Intel® Xeon Phi™ Coprocessor

Covers various parallel programming models like OpenMP, Cilk Plus, and TBB.

Using Intel® MKL

Details how to use the Intel Math Kernel Library for performance optimization.

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