JVC GR-DVA10 Technical Guide

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Deck CPU (IC1401: MN103004KRH) pin functions (2/5)
Pin No. Label In/Out
Description
11 VDDB - Power supply (REG_3V)
37 DK(L) In Servo CPU ready signal (Low: Deck mode)
24 RE(L) Out Read enable signal
38 WE1(L) - Test terminal (TL1401)
12 WE0(L) Out Write enable signal
40 PVDD - Power supply (REG_3V)
53 PVSS - GND
56 MMOD1 -
54 MMOD0 -
55 RESET(L) In Reset input (From SYSCON CPU: IC1001)
70 FRQS - L: fixed
71 VSS - GND
69 EXMOD1 - H: fixed
68 EXMOD0 - H: fixed
72 OSCI In 27MHz clock input (Form TG/V.DRV: IC5501)
88 OSCO - Test terminal (TL1423)
86 VDDH - Power supply (REG_3V)
87 SYSCLK - Test terminal (TL1433)
85 EQ_CS Out Chip select signal (To DV_EQ: IC3201)
104 DV_CS Out Chip select signal (To DECK_DSP: IC3001)
102 CS1(L) - Test terminal (TL1402)
103 CS0(L) - Test terminal (TL1403)
101 VDD - Power supply (REG_3V)
100 ODD_EVEN Out Odd/Even field discrimination signal at slow playback (FRAME ADVANCE)
84 V_PB_L Out Video track area recording off signal
99 DV_RST Out Reset signal output (To DECK_DSP: IC3001)
83 EQ_TRST Out Reset signal output (To DV_EQ: IC3201) (For Boundary scan)
120 EQ_RST Out Reset signal output (To DV_EQ: IC3201)
118 VSS - GND
119 HID_3 Out Head switch pulse (control of recording current measure circuit)
116 REC_I Out ON/OFF control for recording circuit (To PRE/REC IC)
117 PBH Out ON/OFF control for playback circuit (To PRE/REC IC)
134 REEL_LED Out Reel sensor LED control
135 REC_SAFE In REC safety switch
133 VDDH - Power supply (REG_3V)
136 CAM2
132 CAM1
148 CAM0
149 AVSS - GND
152 -
150 -
151 -
147 -
In
- Not used
Control port for FLASH CPU
Mechanism position detect from rotary encoder
Table 2-7-1 Deck CPU (IC1401: MN103004KRH) pin functions (2/5)

JVC GR-DVA10 Specifications

General

Brand	JVC
Model	GR-DVA10
Category	Camcorder
Language	English