© National Instruments Corporation 7 NI 5761R User Guide and Specifications
Clocking
The NI 5761 clocks control the sample rate and other timing functions on the device. Table 3 contains
information about the possible NI 5761 clock resources.
Using Your NI 5761R with a LabVIEW FPGA Example VI
The NI FlexRIO Adapter Module Support software includes a variety of example projects to help get
you started creating your LabVIEW FPGA program. This section explains how to use an existing
LabVIEW FPGA example project to generate and acquire samples with the NI 5761R. This example
requires at least one SMA cable for connecting signals to your NI 5761R.
Note Examples available for your device are dependent on the device-specific minimum software
requirements. For more information about software requirements for your device, visit
ni.com/
info
and enter rdsoftwareversion as the Info Code to determine which minimum software
versions you need for your device.
Each NI 5761R example project includes the following components:
• A LabVIEW FPGA VI that can be compiled and run embedded in FPGA hardware
• A VI that runs in LabVIEW for Windows and interacts with the LabVIEW FPGA VI
Note In NI application software, NI FlexRIO adapter modules are referred to as IO Modules.
Complete the following steps to run an example that acquires a waveform on CH 0 of the NI 5761.
1. Connect one end of an SMA cable to CH 0 on the front panel of the NI 5761 and the other end of
the cable to your device under test (DUT).
2. Launch LabVIEW.
3. In the Getting Started window, click Find Examples to display the NI Example Finder.
4. In the NI Example Finder window, select Hardware Input and Output»FlexRIO»IO Modules»
NI 5761.
5. Select NI 5761 - Getting Started.lvproj.
6. In the Project Explorer window, open NI 5761 - Getting Started (Host).vi under My Computer.
The host VI opens. This VI uses the NI 7952R as the FPGA target by default. If you are using an
NI FlexRIO FPGA module other than the NI 7952R, complete the following steps to change to an
FPGA VI that supports your target.
a. Select Window»Show Block Diagram to open the VI block diagram.
b. On the block diagram, right-click the Open FPGA VI Reference (PXI-7952R) function and
select Configure Open FPGA VI Reference.
Table 3. NI 5761 Clock Sources
Clock Frequency Source Options
Sample Clock 175 MHz to 250 MHz • Internal VCO locked to a Reference clock
• External through the CLK IN connector
• External through IoModSyncClock
Reference Clock 10 MHz • Internal
• External through the CLK IN connector
• External through IoModSyncClock
To Next Page
Loading...
Need help?
General
