NI 5761R User Guide and Specifications 4 ni.com
Block Diagram
Figure 2 shows the NI 5761 block diagram and signal flow to and from the NI 5761 component-level intellectual
property (CLIP) by way of the adapter module and the corresponding NI 5761 CLIP in LabVIEW FPGA.
Figure 2. NI 5761 Connector Signals and NI 5761 CLIP Signal Block Diagram
PFI Input
LabVIEW FPGA CLIPNI 5761 Adapter Module
PFI Output
PFI Write Enable
PFI Connector
Enable
LED <0..3>
Trigger Input
SPI Read
SPI Write
SPI Address
SPI Write Data
SPI Read Data
SPI Device Select
Initialization Done
Reinitialize
Configuration Error
Sample Clock Select
Sample Clock Commit
SPI Idle
Analog FE
IO Module Clock 0
(n = 1, Single Sample CLIP
n = 2, Multiple Sample CLIP)
Multiple
Sample CLIP
Single
Sample CLIP
AI 0
AI 1
AI 2
AI 3
AI 0 Data N
AI 1 Data N
AI 2 Data N
AI 3 Data N
AI 0 Data N–1
AI 1 Data N–1
AI 2 Data N–1
AI 3 Data N–1
Data
Clock
Data
Sample Clock
Clock
Buffer
Internal
Reference
Clock
Clock
Synthesizer
Switch
Buffer
Switch
CLK IN
D<0..3>
(LEDs)
AUX I/O
TRIG
CH 0
CH 1
CH 2
CH 3
Switch
Clock
ADC
Interface
IOModSyncClock
1/n
Switches
ADS62P49
ADS62P49
ADS62P49
Analog
Front End
FET
Buffer
FET
Buffer
8
8
8
8
4
Analog
Front End
Analog
Front End
Analog
Front End
AD9512
AD9512
SPI Engine
Interfacing
with:
Synthesizer Locked
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