Programming Instructions Appendix C
76
Area IR SR HR TR TC DM #
Bits/Words 0000 to 1807 1808 to 1907 HR 000 to 915 TR 0 to 7 TC 00 to 47 DM 00 to DM 63 0000 to 9999
or 0000 to FFFF
Name
Mnemonic
OperandsFunctionSymbol
Shift
Register
SFT(10)
I
P
R
SFT(10)
St
E
Creates a bit shift register from the starting
word (St) through the ending word (E). I:
input bit; P: shift pulse; R: reset input. St
must be less than or equal to E and St and
E must be in the same data area.
E
St
15 150
IN
0
St/E:
IR
HR
AR
LR
Latching
Relay
KEEP(11)
S
KEEP(11)
B
R
Defines a bit (B) as a latch controlled by
set (S) and reset (R) inputs.
B:
IR
HR
AR
LR
Reversible
Counter
CNTR (12)
II
DI
R
N
SV
CNTR(12)
Increases or decreases PV by one when-
ever the increment input (II) or decrement
input (DI) signals, respectively, go from
OFF to ON. SV: 0 to 9999; R: reset input.
Must not access the same TC bit as anoth-
er timer/counter. The TC bit is input as a
constant.
N:
TC
SV:
IR
SR
HR
AR
LR
DM
#
Differentiate
Up
DIFU(13)
Differentiate
Down
DIFD(14)
DIFU(13)
DIFD(14)
B
B
DIFU turns ON the designated bit (B) for
one scan on the rising edge of the input
signal; DIFD turns ON the bit for one scan
on the trailing edge.
B:
IR
HR
AR
LR
High-speed
Timer
TIMH(15)
TIMH
N
SV
A high-speed, ON-delay (decrementing)
timer. SV: 0.01 to 99.99 s; accuracy:
+0/–0.1 s. Must not be assigned the same
TC bit as another timer or counter. The TC
bit is input as a constant.
N:
TC
SV:
IR
SR
HR
AR
LR
HR
#
Word Shift
WSFT(16)
WSFT(16)
E
St
Left shifts data between starting (St) and
ending (E) words in word units, writing zer-
os into starting word. St must be less than
or equal to E and St and E must be in the
same data area.
St/E:
IR
HR
AR
LR
DM
Compare
CMP(20)
CMP(20)
Cp1
Cp2
Compares two sets of four-digit hexadeci-
mal data (Cp1 and Cp2) and outputs result
to GR, EQ, and LE.
Cp1/Cp2:
IR
SR
HR
AR
LR
TC
DM
#
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