EasyManuals Logo
Home>Renesas>Computer Hardware>RL78/F24

Renesas RL78/F24 User Manual

Renesas RL78/F24
58 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #47 background imageLoading...
Page #47 background image
E1/E20/E2/E2 Lite Additional Document 3. Notes on Usage
R20UT1994EJ0900 Rev.9.00 Page
47
of 58
Jan.20.22
3.5.2 Operation for Voltages and Flash Operation Modes Not Permitting Flash Memory Rewriting
When a voltage with which rewriting or erasure of flash memory cannot be performed has been selected or
flash programming has been disabled with the debugger's property, the following debugger operations that
accompany flash memory rewriting will cause an error in the debugger and the operations will be invalidated.
Writing to internal flash memory
Setting or canceling of software breakpoint
Starting execution at the set software breakpoint position
Stepped execution at the set software breakpoint position
Step-over execution, Return Out execution
Execution to the caret position
Setting, changing, or canceling of hardware breaks
Masking/unmasking of internal reset
Switching of peripheral breaks
Setting or canceling a monitoring point (extended function of the E2)
The operating frequency range and operating voltage range are set with the flash operation mode. Correct
operation may not be carried out when the operating frequency range or operating voltage range is
exceeded.
3.6 GDIDIS
The global digital input disable register (GDIDIS) is used to prevent through-current flowing from the input
buffers when the EVDD power supply is turned off (EVDD = 0 V). Since this also disables communications
through the TOOL0 pin when the E1/E20/E2/E2 Lite is in use, do not set GDIDIS to 1 (prohibiting input to the
input buffers).
3.7 RESET# Multiplexed Pin
In the RL78/G11 and the 20- and 24-pin versions of the RL78/G12, the RESET# pin has multiplexed pin
functions. Therefore, if the following conditions are all satisfied, control by the E1/E20/E2/E2 Lite is no longer
possible.
The reset/port multiplexed pin is used as a port (PORTSELB = 0) due to the option byte setting (C1h).
The option byte setting (C1h) has been rewritten during a break.
"Yes" is selected in the [Mask INTERNAL RESET signal] property of the debugger.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Renesas RL78/F24 and is the answer not in the manual?

Renesas RL78/F24 Specifications

General IconGeneral
BrandRenesas
ModelRL78/F24
CategoryComputer Hardware
LanguageEnglish

Related product manuals