AN4488 Rev 7 29/50
AN4488 Debug management
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5 Debug management
The Host/Target interface is the hardware equipment that connects the host to the
application board. This interface is made of three components: a hardware debug tool, a
JTAG or SW connector and a cable connecting the host to the debug tool.
Figure 13 shows the connection of the host to the evaluation board.
Figure 13. Host-to-board connection
5.1 SWJ debug port (serial wire and JTAG)
The STM32F4xxxx core integrates the serial wire / JTAG debug port (SWJ-DP). It is an
Arm
®
standard CoreSight™ debug port that combines a JTAG-DP (5-pin) interface and a
SW-DP (2-pin) interface.
• The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port
• The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
For more details on the SWJ debug port refer to the reference manual of the product, SWJ
debug port section (serial wire and JTAG).
5.2 Pinout and debug port pins
The STM32F4xxxx MCU is offered in various packages with different numbers of available
pins. As a result, some functionality related to the pin availability may differ from one
package to another.
5.2.1 SWJ debug port pins
Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose
I/Os (GPIOs). These pins, shown in
Table 8, are available on all packages.
%VALUATIONBOARD
(OST0#
0OWERSUPPLY
*4!'37CONNECTOR
$EBUGTOOL
AIB
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