Recommended PCB routing guidelines for STM32F4xxxx devices AN4488
36/50 AN4488 Rev 7
8 Recommended PCB routing guidelines for
STM32F4xxxx devices
8.1 PCB stack-up
In order to reduce the reflections on high speed signals, it is necessary to match the
impedance between the source, sink and transmission lines. The impedance of a signal
trace depends on its geometry and its position with respect to any reference planes.
The trace width and spacing between differential pairs for a specific impedance requirement
is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace
width and spacing which depend on the type of PCB technology and cost requirements, a
PCB stack-up needs to be chosen which allows all the required impedances to be realized.
The minimum configuration that can be used is 4 or 6 layers stack-up. An 8 layers boards
may be required for a very dense PCBs that have multiple SDRAM/SRAM/NOR/LCD
components.
The following stack-ups are intended as examples which can be used as a starting point for
helping in a stack-up evaluation and selection. These stack-up configurations are using a
GND plane adjacent to the power plane to increase the capacitance and reduce the gap
between GND and power plane. So high speed signals on top layer will have a solid GND
reference plane which helps to reduce EMC emissions, as going up in number of layers and
having a GND reference for each PCB signal layer will improve further the radiated EMC
performance.
Figure 21. Four layer PCB stack-up example
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