RPREDSG
RPULLUP2
DSGCHG
VCC
PACK+
CELL+
bq76200
bq78350
RPULLUP1
GPIO_B
RDIVIDE
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Added Features
3
SLUUBM6–March 2018
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Overview
Figure 1. PRE-DISCHARGE
If the DSG FET is off and the bq78350-R2 device receives a request to turn it on, and if the bq78350 does
not detect a charging current above a level of Charge Current Threshold, the bq78350-R2 device will
first enter a pre-discharge phase for a length of time given by Pre-Discharge:[FET ON Time]. After this
time expires, the bq78350-R2 device will disable the pre-discharge phase and turn on the DSG FET.
If the DSG FET is off and the bq78350-R2 device receives a request to turn it on, and if the bq78350-R2
device detects a charging current above a level of Charge Current Threshold, the bq78350-R2 device
will immediately turn on the DSG FET and not first implement a pre-discharge phase.
While the bq78350-R2 device is in the pre-discharge phase, if any fault or issue occurs that would
normally cause the DSG FET to be disabled (such as ACSD, AOLD, OTD, UTD), then the bq78350-R2
device will immediately disable the pre-discharge phase but keep the DSG FET off until all such faults are
cleared.
3.1.1 Flash Changes for PRE-DISCHARGE Mode
Data flash bits to enable/disable the pre-discharge functionality and control the polarity of the signaling
used on GPIO_B are included in the FET Options register.
Class Subclass Name Format
Size in
Bytes
Min Max Default Unit
Settings Configuration FET Options Hex 2 0x0000 0xFFFF 0x0021 —
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
High byte RSVD RSVD RSVD RSVD PDSG_POL PDSG_EN KEY_POL PCHG_POL
Low Byte RSVD SLEEPCHG CHGFET CHGIN CHGSU OTFET KEY_EN PCHG_EN
RSVD (Bits 7–4): Reserved
PDSG_POL: Configures the bq78350-R2 device GPIO_B pin output polarity when used for PRE-
DISCHARGE mode. If PDSG_EN = 0, then this bit has no influence.
0 = The bq78350-R2 device configures the GPIO_B as active low (default).
1 = The bq78350-R2 device configures the GPIO_B as active high, requiring an external pull up.
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