3.2 Control Mapping
Figure 3-2 shows the digital control signal mapping between processor and PMIC devices. For the two PMIC
devices to work together, the primary PMIC and secondary PMIC must establish an SPMI communication
channel. This allows the two TPS6594-Q1 to synchronize their internal Pre-Configurable State Machines (PFSM)
so that they operate as one PFSM across all power and digital resources. The GPIO_5 and GPIO_6 pins on the
TPS6594-Q1 are assigned for this functionality. In addition, the LDOVINT pin of the primary PMIC is connected
to the ENABLE pin of the secondary PMIC in order to correctly initiate the PFSM.
Other digital connections from the TPS6594-Q1 PMICs to the processor provide error monitoring, processor
reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals
in order to ensure proper operation during low power modes when only a few GPIO pins remain operational.
The digital connections shown in Figure 3-2 allow system features including 'MCU-only, MCU Safety Island' and
DDR Retention modes, functional safety up to ASIL-D, and compliant dual voltage SD card operation.
www.ti.com Processor Connections
SLVUC99 – JANUARY 2022
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Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
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Copyright © 2022 Texas Instruments Incorporated
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