Alto Hardware Manual
Section 2: Microprocessor
7
interface cannot process the function
(MAR
<-,
MD<-
or
<-
MD)
specified; processing will resume
as
soon
as
the interface
is
free.
It
is
permissible to "abandon" a memory reference that has
already been started simply
by
not referencing
MD
within the first 5 cycles, or by starting a
new memory reference
with
MAR
~
.
c)
The memory checks parity
on
all fetches, unless the cycle
is
a refresh cycle or the address is
between
177000B
and
177777B
inclusive, in which case an
I/O
device is being referenced.
Parity errors result in activation
of
a high-priority task (task number
15B)
whose purpose is to
deal with the error (see section 5.5). The Alto II checks memory parity on store
as
well as
fetch cycles.
d)
If
RSELECT
=
37B
during the instruction which starts the memory, a refresh cycle
is
assumed
and all memory cards are activated.
. This
is
used by the refresh task.
e)
MAR<-
cannot be invoked
in
the same instruction
as
<-MD
of
a previous access.
In the discussion that
follows,
we
assume that a memory reference has been started with
MAR
<-,
and
we
designate this instruction (micro)cycle
1.
Examples
of
proper sequences are given below.
Alto I
Alto
II
f)
During cycle
5,
if
F2=6,.
MD<-,
a store
of
bus data into the word addressed by
MAR
will
occur. The
MD<-
may not
be
issued later than cycle
5.
(Note: Some Alto
1's
have been
modified to
allow
a "double-word store."
On
these machines, it
is
permissible to issue two
MD<-
instructions in a row, the first coming in cycle
5,
and the second in cycle
6.
If
MAR
is
loaded with an even address adr, the two words will be stored
at
adr and
adr+
1
respectively.)
g)
During cycle 5
of
a reference,
if
BS
=
5,
<-
MD,
the reference
is
a fetch
of
the word addressed
by
MAR.
During cycle
6,
if
BS
=
5,
<-
MD,
the odd word
of
the doubleword addressed by
MAR
is
delivered.
If
MD
is
referenced during cycle
6,
it also must have been referenced (by either
+-MD
or
MD+-)
during
cycle
5.
f)
During cycle
4,
if
F2=6,
MD<-,
a store
of
bus data into the word addressed by
MAR
will
occur. The
MD<-
may not be issued later than cycle
4.
Alto II's allow a "double-word
store:" it
is
permissible to
issue
two
MD<-
instructions in a row, the first coming in cycle
3,
and the second in cycle
4.
If
MAR
is
loaded with an address adr, the two words will
be
stored at adr and (adr
XOR
1)
respectively.
g)
During cycle
5,
if
Bs=5,
<-MD,
the reference
is
a fetch
of
the word addressed by
MAR.
During cycle
6,
if
Bs=5,
<-MD,
the other word
of
the doubleword addressed by
MAR
is
delivered. Again,
if
MAR
is
loaded with address adr, the two words fetched
will
be
from
location adr and (adr
XOR
1) respectively.
h) Because the Alto II latches memory contents, it
is
possible to execute
<-
MD
anytime after cycle
5
of
a reference and obtain the results
of
the read operation.
EXAMPLES
Because the description above
is
a bit terse,
we
shall give several examples for Alto I operation, for Alto
II operation, and for coding schemes that will work properly on both kinds
of
Altos. In the coding
examples,
REQUIRED
stands for some microinstruction (you supply
it)
that must appear in the sequence;
SUSPEND
stands for a microinstruction which
if
omitted
will
cause execution to suspend for one cycle
because the memory interface
is
not ready;
OPTIONAL
stands for a microinstruction which may
be
omitted without penalty. The notation
ANY
will be used to stand for an arbitrary 16-bit address;
EVEN
will stand for an even 16-bit address.
All
of
these examples apply to extended memory references also
(described in the next section); simply substitute
XMAR
for
MAR.
To Next Page
Loading...
Need help?
General
