Alto Hardware Manual Section
4:
Display Controller
33
function (F2=10B, specific to the display word
task
DWT,
illegal in an instruction which stops the clocks).
The purpose
of
the intermediate buffer
is
to
synchronize data transfers between the main buffer, which
is
synchronous with ·the
170ns.
master clock, and the shift register, which is clocked with
an
asynchronous
bit clock. The
sync
generator provides this clock and the vertical and horizontal synchronization signals
required
by
the monitor .
. The bit
clock
is
disabled
by
vertical and horizontal blanking, and its rate can be set by the microcode
to
either
50
or
100
ns.
by the function
SETMODE
(F2
= llB, specific to the display horizontal task
DHT).
This
function examines the
two
high order bits
of
the processor
bus.
If
bit
0=1,
the
bit
clock rate
is
set to
lOOns
period (at the start
of
the next scan line), and a 1 is merged into
NEXT[9].
SE1MODE
also latches bit
1
of
the processor bus and uses the value to control the polarity
of
the video output. A third function,
EVENFIELD
(F2
=
lOB,
specific to
DHT
and
to
the display. vertical task
DVT),
merges a 1 into
NEXT[9]
if
the
display
is
in
the even field.
The display control hardware also generates·
wakeup
requests to the microprocessor tasking hardware.
The vertical
task
DVT
is
awakened once per
field,
at the beginning
of
vertical retrace. The display
horizontal
task
is
awakened once at the beginning
of
each field, and thereafter whenever the display
word task blocks.
DHT
can block itself, in which
case
neither it nor the word task can
be
awakened until
the start
of
the next field. The wakeup request for the display word task
(DWT)
is
controlled by the state
of
the
16
word
buffer.
If
DWT
has not executed a
BLOCK,
if
DHT
is not blocked,
and
if
the buffer is not
full,
DWT
wakeups are generated. The hardware
sets
the buffer empty and clears the
DWT
block flip-flop
at the beginning
of
horizontal retrace for
every
scan line.
4.3
Display Controller Microcode
. The display controller microcode is divided into three tasks. The highest prioiitytask is
DVT,
the display
vertical
task,
the next
is
DHT,
the horizontal task, and the third is
DWT,
the display word task. The
display controller uses 6 registers in
R:
CBA:
Holds the address
of
the currently active
DCB+
1.
AECL:
Holds the address
of
the end of the currently active scan line's
bit
map in main
memory.
SLC:
Holds the number of scan lines remaining in the currently active
DCB.
HTAB:
Holds the number of tab
words
remaining on the current scan line.
DWA:
Holds the address
of
the bit map doubleword currently being fetched for
transmission to the hardware buffer.
MTEMP:
Is
a temporary
cell.
The vertical task initializes the controller by setting
SLC
to 0 and
CBA
to
DASTART+
1.
It
also merges the
contents
of
DASTART+
1 into NWW, which
will
cause
an interrupt
if
the specified channel is active.
DVT
also sets up information required for the cursor
(see
below),
TASKS
and becomes inactive until the next
field.
DHT
starts
by
initiating a fetch to the word addressed by
CBA.
It
checks
SLC,
and
if
it is zero, the
controller
is
finished with the current
DCB,
and the link word
of
the
DCB
is fetched.
If
this word is non-
zero, it replaces
CBA
and processing
of
a
new
DCB
is
begun.
If
the link word
is
zero,
DHT
blocks until
the start
of
the next
field.
If
the check
of
SLC
indicates that more scan lines remain in the current
DCB,
SLC
is decremented by one·
and the fetch
of
(CBA)
is
used to obtain the second word
of
the
DCB,
rather than the link word. The
contents
of
this word are used to set the display mode and polarity, and the tab count is extracted and
put into
HTAB.
NWRDS
is
extracted, and used to increment
DWA
and
AECL
by
the appropriate amount,
depending on the mode and field. All the registers required by
DWT
have now been set up, and
DHT
TASKS
and becomes inactive until
DWT
blocks.
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