Alto Hardware Manual Section 5: Miscellaneous Peripherals
40
MESR[0-5]
Hamming code reported
from
error
MESR[6]
. Parity Error
MESR[7]
Memory parity bit
MESR[8-13]
Syndrome bits
MESR[14-15]
Bank number in which error occurred
MESR[14-15]
is
an extension to the most significant end
of
MEAR.
This field
is
only present
if
the
extended memory option
is
installed (see section 2.3), otherwise it reads out
-1.
Memory Error Control Register
(MECR
=
177026B).
Storing into this register is the means for
controlling the memory error
logic.
This register
is
set to all ones (disable all interrupts) when the Alto
is
bootstrapped and when the parity error task first detects an error. When an error has occurred,
MEAR
and
MESR
should
be
read before setting the
MECR.
Bits
are "low true,"
Le.
a 0 bit enables the condition.
MECR[O-
3]
Spare
MECR[4-10]
Test Hamming code (used only for special diagnostics)
MECR[ll]
Test mode (used only for special diagnostics)
MECR[12]
Cause interrupt on single-bit errors
if
zero
MECR[13]
Cause interrupt on double-bit errors
if
zero
MECR[14]
Do not use error correction
if
zero
MECR[15]
Spare
Note that
MECR[12].
and
[13]
govern only the initiation
of
interrupts;
MEAR
and
MESR
hold information
about the first error that occurs after reseting
MESR
regardless
of
what kind
of
errors are to cause
interrupts.
ADDRESS
MAPPING
The mapping
of
addresses to memory chips can be altered
by
the setting
of
the "memory configuration
switch." This switch is located on the front
of
Alto
1's,
and at the top
of
the backplane
of
the Alto II.
The current setting
of
the switch
is
reported in bit 6
of
UTILIN
(location
177030B):
if
this bit
is
0,
the
switch is in the "normal" position ("up" on Alto
I,
"back" on Alto II), otherwise the switch is in
the
"alternate" position. On Alto I,
if
the switch
is
in the alternate position, the first two
16K
portions
of
memory are exchanged
(i.e.,
the memory address
is
modified by the algorithm:
if
MAR[O]
= 0 then
MAR[l]+-MAR[l]
XOR
1).
On Alto II,
if
the switch
is
in the alternate position, the first and second 32K
portions
of
memory are exchanged
(Le.,
the memory address
is.
modified by the algorithm:
MAR[O]+-MAR[O]
XOR
1).
In order
to
fix many memory problems, it
is
necessary to know the mapping between memory admesses
(and bit numbers) to actual memory chips on the memory boards. Herewith the mapping, given in the
style
of
a program: the algorithm
is
given the memory address
(address)
and the bit position in the word
(bit).
The function odd(x) returns true
if
the 16-bit number x
is
odd. The variable switch corresponds to
the setting
of
the memory configuration switch
(Le.,
switch
+-UTILIN[6]).
.
Alto I
The variables
row
and
column
are the "coordinates"
of
the memory chip on the given cardSlot, as printed
by
the memory diagnostic. The chipNumber is the chip number on the memory board. Bit
16
is the
parity bit.
if address[O]=O then (if
switch=l
then address[l]+-address[l] xor 1)
row
+-
address[2-4]
cardSlot+-(address[0-1])*4 +
13
if
odd(address) then card+-card+2
column
+-
bit
if
bit
~
12 then [ card+-card+1; column+-bit-5 ]
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