H_PROCHOT#[36]
S
D
G
Q36B
*MTDK5S6R
5
3
4
R91 * 100K_04
CLK_DP_N [13]
CLK_D P_P [13]
C22
0.047u_10V_X7R_04
S3 circuit:- DRAM PWRGOOD logic
PM_DR AM_PWR GD[14]
PMSY S_PWRG D_BUF
1.5V_CPU
R57
10K_04
D02 1114
R857 *10mil_04
S
D
G
Q36A
*MTDK5S6R
2
6
1
R530 *10K_04
CLOCKS
MISC
THERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U34B
P31X24_1023B_01B
SM_RC OMP[1]
BE43
SM_RC OMP[2]
BG43
SM_DR AMRST#
AT30
SM_RC OMP[0]
BF44
BCLK#
H2
BCLK
J3
DPLL_REF_CLK#
AG1
DPLL_REF_CLK
AG3
CATERR#
C49
PECI
A48
PROC HOT#
C45
THE RMTR I P#
D45
SM_DR AMPWROK
BE45
RESET#
D44
PRDY#
N53
PREQ#
N55
TC K
L56
TMS
L55
TRS T#
J58
TD I
M60
TD O
L59
DBR#
K58
BPM#[0]
G58
BPM#[1]
E55
BPM#[2]
E59
BPM#[3]
G55
BPM#[4]
G59
BPM#[5]
H60
BPM#[6]
J59
BPM#[7]
J61
PM_SY NC
C48
PROC _SELECT#
F49
UNCOREPWRGOOD
B46
PROC _DETECT#
C57
R59 *1 0mil_04
C515
47p_50V_NPO_04
H_PROCHOT#
R60 130_ 1%_04
CAD Note: C apacitor
need to be placed
close to bu ffer output pin
H_PROCHOT_EC[27]
Q14
2SK3018S3
G
DS
PMSYS_PWRGD_BUF
R414 *5 1_04
R416 *5 1_04
R108 *5 1_04
R415 *5 1_04
R109 *5 1_04
R95 51_04
3.3VS
VTT_CPU
XD P_D B R_ R
R407 *1 K_04
XD P_T MS
XD P_T DO _R
PU/PD for JTAG signals
XD P_T RS T#
XD P_P R EQ #
XD P_T DI _R
XD P_T CL K
H_CPUPWRGD_R
R106
750_1%_04
R112 1.5K_1%_04
Processor Pullups/Pull downs
TRACE WIDTH 10MIL, LENGTH <500MILS
3.3VS
BUF_CPU_RST#
DDR3 Compensation Signals
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
C96
*68p_50V_NPO_04
VDDPWRGOOD_R
XDP_TRST#
XDP _TCL K
PLT_RST#[10,16,22]
XDP _TMS
XDP _TDI _R
CPUDRAMRST#
H_PROCHOT#_D
H_CATERR#
Buffered reset to CPU
XDP _TDO _R
XDP_PR EQ#
H _THR MTR IP #[17]
H_SNB_IVB#[17]
R382 25.5_1%_04
R381 200_1%_04
R419 *10mil_04
R412 10K_04
R413 140_1%_04
H_PECI[17,27]
PM_SYNC_R
If PROCHOT# is not used, then it must
be terminated with a 68-£[ +-5%
pull-up resistor to 1.05VS_VTT .
Ivy/Sandy Bridge Processor 2/7
( CLK,MISC,JTAG )
R418 *10mil_04
R410 6 2_04
VTT_CPU
H_PROCHOT#
SM_RCOMP_2
SM_RCOMP_0
SM_RCOMP_1
CLK_EXP_N [13]
CLK_EXP_P [ 13]
H_PM_SYNC[ 14]
1.5V[9,19,31,33]
1.5V_CPU[5,6,31]
VTT_CPU[2, 5,6,17, 18,19,34, 35]
3.3V[2, 6,10,12,13,14,16,17, 18,19,21, 22,25,27, 31,33,34,35]
H_CPUPWRGD[17]
Q8
2SK3018S3
G
DS
R46
4.99K_1%_04
CPUDRAMRST#
R47 * 0_04
1.5V
R45
1K_04
S3 circuit:- DRAM_RST# to memory
should be high during S3
DRAMRST_CNTRL [13]
DDR3_DRAMRST# [9]
R48 1K_04
XDP_DBR_R
R411 *10mil_04
XDP_BPM1_R
XDP_BPM0_R
XDP_BPM6_R
XDP_BPM5_R
XDP_BPM4_R
XDP_BPM3_R
XDP_BPM2_R
XDP_BPM7_R
H_PECI _R
R105 *75_1%_04
R405 56_1%_04
R859 *10mil_04
D02 1126
H_CPUPWRGD_R
H_PROCHOT#
R104 *43_1%_04
R531
*100K_04
C585 0.1u_1 0V_X7R_04
XDP _PR DY #
VTT_CPU
3.3VS[9,10,11,12,13,14,15,16,17, 18,19,21, 22,23,24, 27,28,29, 30,31,36]
R417 *10mil_04
H_THRMTRIP#_R
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