C508
*0.1u_16V_Y5V_04
C285
*0. 1u_16V_Y5V_04
C294
*0.1u_16V_Y5V_04
***
AC coupling close to
connector (<100 mils)
S
D
G
Q124A
MTDK5S6R
2
6
1
PLT_RST#
60mils
D02 1218
UIM_RST
R878
10_06
3G_3.3V
KEY
J_3G1
88910-5204M-01
COEX1
3
COEX2
5
CLKREQ#
7
GND0
9
REFCLK-
11
REFCLK+
13
WAKE#
1
GND1
15
PETn0
23
PETp0
25
GND2
21
GND3
27
PERn0
31
PERp0
33
GND4
29
Reserved0
17
Reserved1
19
W_D ISABLE#
20
GND12
37
3.3VAUX_3
39
3.3VAUX_4
41
GND13
43
Reserved2
45
Reserved3
47
Reserved4
49
Reserved5
51
LED_WLAN#
44
LED_WW AN#
42
GND6
18
UIM_VPP
16
UIM_RESET
14
3.3VAUX_0
2
UIM_CLK
12
UIM_DATA
10
UIM_PWR
8
1.5V_0
6
GND5
4
PERSET#
22
3.3VAUX_1
24
GND7
26
1.5V_1
28
SMB_CLK
30
SMB_DATA
32
GND8
34
USB_D -
36
USB_D+
38
GND9
40
LED_W PAN#
46
1.5V_2
48
GND10
50
3.3VAUX_2
52
GND11
35
>120 mil
R880 330K_04
C235
0.1u_16V_Y 5V_04
R348, R615, R725, R861, R862,
R863, R864, X8, C302,
C305¤W¥ó
SLB9635 (1.2)
SLB9655 (1.2)
default
3G POWER
UIM_DATA
Q78 MTP3415KN3
G
DS
>120 mil
3.3V
UIM_VPP
C736
0.1u_16V_Y 5V_04
C735
1u_10V_Y5V_06
UIM_RST
UIM_PWR
C737
0.1u_16V_Y 5V_04
3G_PWR_EN[27]
3G_3.3V
UIM_CLK
C267
10u_10V_Y5V_08
3G_3.3V
3G_3.3V
R879
100 K_04
3G_DET#[27]
3G_3.3V
60mils
USB_PP11 [16]
USB_PN11 [16]
UIM_DATA
C212
0.1u_16V_Y5V_04
SIM CONN
UIM_CLK
MINI CARD 3G/mSATA(Port 6)
*
C470
*22p_50V_NPO_04
C469
*22p_50V_NPO_04
3.3VS[3, 9,10,11,12,13,14,15,16, 17,18,19,21,23, 24,27,28,29,30,31, 36]
C471
*22p_50V_NPO_04
3.3V[2,6,10,12,13, 14,16,17,18, 19,21,25,27, 31,33,34,35]
SLB9635 (1.2)
C242
0.1u_16V_Y 5V_04
R503 *4.7K_04
C489
*22p_50V_NPO_04
L: NORMAL ( Int. PD )
SIMLOCK
UIM_VPP
C209
0.1u_16V_Y5V_04
1. SIM¤§©Ò¦³«H¸¹½u¥[²Ê(10mil)
2. ©Ò¦³«H¸¹½u¤§¶¡¥[GND
3. SIM
HOLD¥»Åé¥|©P¥[ GND³ò ¶
LAYOUT NOTE:
(TOP VIEW)
J_SIM1
*91712-0090P
UIM_DATA
7
UIM_VPP
4
UIM_GND
2
UIM_PWR
1
UIM_RST
3
UIM_CLK
5
GNG
GND1
UIM_I/O
6
UIM_MCMD
8
DETECT_SW
9
GND
GND2
GND
GND3
GND
GND4
D02 1217
+
C287
220U_4V_D2_D
SATATXN4[12]
¡¶ 3G only:J_SIM1, C286,
C287
3. 3VS
D02 1114
*
SATATXP4[12]
X8
*MC-306_32.768KHz
14
3 2
C305
*18p_50V_NPO_04
C302
*18p_50V_NPO_04
LPC _AD1[ 12,27]
LPC _AD2[ 12,27]
PLT_RST#[3,10,16]
LPC _AD3[ 12,27]
SERI RQ[12,27]
LPC _AD0[ 12,27]
PCLK_TPM[16]
LPC_FRAME#[12,27]
S4_ STATE#[14]
PM_CLKRUN#[14]
PL T_RS T#
TPM3005
TPM_BAD D
TPM3002
TPM
U28
*SLB9655TT
LAD3
17
LAD0
26
LAD1
23
LAD2
20
VDD1
10
XTA L I
13
VDD3
24
VDD2
19
LFRAME#
22
LCLK
21
LRESET#
16
SERI RQ
27
CLKRUN#
15
GND_1
4
GND_2
11
GND_3
18
GND_4
25
GPIO
6
GPIO2
2
XTA LO
14
TESTI
8
TESTBI/BADD
9
PP
7
NC_1
1
NC_2
3
NC_3
12
LPCPD#
28
VSB
5
TPM3001
TPM3004
TPM_PP
TPM3003
R612 *0_04
R861 *0_04
TPM 9635 & 9655 co-lay
PN: 6-86-2B010-001
91712-0090P
R862 *0_04
R724 *0_06
VDD3
3. 3VS
R725 *0_06
L: 2E/ 2F H
H: 4 E/ 4F H
LPCPD# inactive to LRST# inactive 32~96us
Asserted before entering S3
LPC reset timing:
6-03-09635-0H3 (1.2) FW¡G3.17
6-03-09655-0H1 (1.2) FW¡G4.31
XTA LO
C282
*0. 1u_16V_Y5V_04
*
PCLK_TPM PCLK_TPM1
C292 *10p_50V_NPO_04R349 *33_04
D02 1114
C645 0.01u_16V_X7R_04
C648 0.01u_16V_X7R_04
C647 0.01u_16V_X7R_04
C646 0.01u_16V_X7R_04
TPM_BAD D
¥´ * ªº¹s¥ó-n¤W¥ó¡A¥]§t¡G
PCLK_TPM¡GR214(P17)
PJ47 *OPEN_3mm
1 2
3G_EN [27]
+
C286
220U_4V_D2_D
¡¶
De f au lt
SATARXP4[12]
R864 *0_04
R615 *10K_04
S4_STATE#_R
H: ACCESS
TPM_PP
TPM_BADD
R613 *10K_04
R348 *10K_04
R352 *10K_04
R341 *10K_04
3.3VS
TPM_B AD D
VDD 3
SATARXN4[12]
UIM_PWR
¡¶
S
D
G
Q124B
MTD K5S 6R
5
3
4
R724, R860,
R902¤W¥ó
60mils
VDD 3[12,21,23, 25,27,28,31,32, 38]
XTA LI
¡¶
PJ47 for RF debug
R860 *0_04
S4_STATE#_R
TPM_P P
De f au lt
D02 1225
R902 *0_04
R863 *0_04
W/ TPM¡G
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