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1 Introduction
This manual documents the features and operation of the HP 2100 simulator. It is intended for use in conjunction
with the SIMH Users' Guide manual, which describes how to compile and run the simulator, as well as the general
commands that may be entered at the Simulation Control Program (SCP) prompt.
1.1 The HP 21xx/1000 Computer Systems
Hewlett-Packard sold the HP 21xx/1000 family of real-time computers from 1966 through 2000. There are three
major divisions within this family: the 21xx core-memory machines, the 1000 (originally 21MX) M/E/F-Series
semiconductor-memory machines, and the 1000 L/A-Series distributed-I/O machines. All machines are 16-bit
accumulator-oriented CISC machines running the same base instruction set. A wide range of operating systems
run on these machines, from a simple 4K word paper-tape-based monitor to a megaword multi-user,
multiprogramming disc-based system and a multi-user time-shared BASIC system.
Within each division, several distinct models were produced:
• the HP 2116; introduced in 1966, expandable to 32 K words (originally 16 K words).
• the HP 2115 (1967); slower, more I/O-limited, expandable to 8 K words.
• the HP 2114 (1968); low-cost, still-more-limited expandability, expandable to 8 K words.
• the HP 2100 (1971); user-microprogrammable, optional floating-point instructions, expandable to 32 KW.
• the HP 21MX (1974, renamed 1000 M); memory-mapped, larger instruction set, expandable to 1024 KW.
• the HP 21MXE (1976, renamed 1000 E); faster CPU and memory, larger microprogram address space.
• the HP 1000 F-Series (1979); an E-Series CPU with a separate hardware floating-point processor.
• the HP 1000 L-Series (1979); low-cost, slower, distributed I/O system, limited to 32K words.
• the HP 1000 XL-Series (1980); an L-Series CPU with memory mapping, expandable to 256 KW.
• the HP 1000 A600 (1982); E-Series speed with L-Series distributed I/O, expandable to 2048 KW.
• the HP 1000 A700 (1982); an A600 with an optional hardware floating-point processor.
• the HP 1000 A900 (1983); faster pipelined processor, cache memory, expandable to 3072 KW.
• the HP 1000 A400 (1986); lower-cost, limited I/O expandability, expandable to 2048 KW.
• the HP 1000 A990 (1991); fastest and last 1000 made, expandable to 4096 KW.
HP claimed the relative CPU performance, normalized to a 1000 E-Series, as follows:
2114 2115 2116 2100 1000 M 1000 E 1000 F 1000 L A400 A600 A700 A900 A990
0.22 0.37 0.42 0.55 0.45 1.0 1.4 0.3 1.1 1.0 1.67 3.3 6.7
All of the machines support a 15-bit logical address space, addressing a maximum of 32 K words, divided into 1K-
word pages. Memory-referencing instructions in the base set can directly address the 1024 words of the base page
(page 0) or the 1024 words of the current page (the page containing the instruction). The instructions in the
extended set directly address the 32768 words in the full logical address space. The A and B accumulators may be
addressed as logical addresses 0 and 1, respectively.
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