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Motherboard Users Guide
PCI Master 0 WS Write
This item determines whether the chipsets inserts a delay before any writes from
the PCI slots. If it is enabled, write requests to the PCI bus are executed immedi-
ately (with zero wait states), if the PCI bus is ready to send data.
PCI Delay Transaction
This item is used to meet the latency of PCI cycles to and from the ISA bus.
VLink mode selection
This item controls the data transfer speed between the north and south bridge.
VLink 8X Support
Use this item to enable or disable VLink 8X support.
DRDY_Timing
This item specifies the timing of data ready.
System BIOS Cacheable
Enable this item to get faster system BIOS executing speed via the L2 cache.
Video RAM Cacheable
Disable or enable this item to read cache data from RAM.
Integrated Peripherals Page
These options display items that define the operation of peripheral
components on the system’s input/output ports.
Phonex-AwardBIOS CMOS Setup Utility
Integrated Peripherals
Help Item
f
f
f
Menu Level
f
VIA OnChip IDE Device [Press Enter]
VIA OnChip PCI Device [Press Enter]
Super IO Device [Press Enter]
: Move Enter: Select +/-/: Value F10: Save Esc: Exit
F1: General Help F5: Previous Values F6: Fial-Safe Defaults F7: Optimized Defaults
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