46 IBM Power 720 and 740 Technical Overview and Introduction
Table 2-1 summarizes the technology characteristics of the POWER7+ processor.
Table 2-1 Summary of POWER7+ processor technology
2.1.2 POWER7+ processor core
Each POWER7+ processor core implements aggressive out-of-order (OoO) instruction
execution to drive high efficiency in the use of available execution paths. The POWER7+
processor has an Instruction Sequence Unit that is capable of dispatching up to six
instructions per cycle to a set of queues. Up to eight instructions per cycle can be issued to
the instruction execution units. The POWER7+ processor has a set of 12 execution units:
Two fixed point units
Two load store units
Four double precision floating point units
One vector unit
One branch unit
One condition register unit
One decimal floating point unit
The following caches are tightly coupled to each POWER7+ processor core:
Instruction cache: 32 KB
Data cache: 32 KB
L2 cache: 256 KB, implemented in fast SRAM
Technology POWER7+ processor
Die size 567 mm
2
Fabrication technology 32 nm lithography
Copper interconnect
Silicon-on-Insulator
eDRAM
Processor cores 3, 4, 6, or 8
Maximum execution threads core/chip 4/32
Maximum L2 cache core/chip 256 KB/2 MB
Maximum On-chip L3 cache core/chip 10 MB/80 MB
DDR3 memory controllers 1
SMP design-point 32 sockets with IBM POWER7+ processors
Compatibility With prior generation of POWER processor
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