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CELERON 1.10 GHZ
Intel CELERON 1.10 GHZ User Manual
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Intel
®
Celeron
®
Process
or up to 1.10
GHz
10
Datasheet
This page is intentionally left blank.
9
11
Table of Contents
Table of Contents
3
Revision History
9
Introduction
11
Terminology
11
Package Terminology
12
Processor Naming Convention
13
Processor Identification
13
References
14
Electrical Specifications
15
System Bus and Vref
15
Clock Control and Low Power States
15
Normal State-State 1
16
Autohalt Power down State-State 2
16
Clock Control State Machine
16
Stop-Grant State-State 3
17
Halt/Grant Snoop State-State 4
17
Sleep State-State 5
17
Deep Sleep State-State 6
18
Clock Control
18
Power and Ground Pins
18
Phase Lock Loop (PLL) Power
19
Processor Decoupling
19
System Bus AGTL+ Decoupling
19
Package
19
Voltage Identification
20
Voltage Identification Definition
20
System Bus Unused Pins
21
Processor System Bus Signal Groups
21
Intel ® Celeron ® Processor System Bus Signal Groups
22
Asynchronous Vs. Synchronous for System Bus Signals
23
System Bus Frequency Select Signal (BSEL[1:0])
23
Test Access Port (TAP) Connection
23
Maximum Ratings
23
Processor DC Specifications
24
Absolute Maximum Ratings
24
Voltage and Current Specifications
25
AGTL+ Signal Groups DC Specifications
31
Non-AGTL+ Signal Group DC Specifications
32
AGTL+ System Bus Specifications
33
Processor AGTL+ Bus Specifications
33
System Bus AC Specifications
34
System Bus AC Specifications (Clock) at the Processor Edge Fingers (for S.E
35
System Bus AC Specifications (Clock) at the Processor Core Pins (for both S.E.P. and PGA Packages)
36
Valid Intel ® Celeron ® Processor System Bus, Core Frequency
38
System Bus AC Specifications (AGTL+ Signal Group) at the Processor Edge Fingers (for S.E
39
System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for S.E
39
Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for PPGA Package)
40
System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for FC-PGA/FC-PGA2 Packages)
40
System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers (for S.E
41
System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins (for both S.E.P., PGA, and FC-PGA/FC-PGA2 Packages)
41
System Bus AC Specifications (CMOS Signal Group)
42
System Bus AC Specifications (Reset Conditions) (for both S.E.P. and PPGA Packages)
42
System Bus AC Specifications (Reset Conditions)
42
System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge Fingers (for S.E
43
System Bus AC Specifications (APIC Clock and APIC I/O)
43
System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core Pins (for S.E.P. and PGA Packages)
44
System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers (for S.E
45
System Bus AC Specifications (TAP Connection) at the Processor Core Pins (for both S.E.P. and PPGA Packages)
46
System Bus AC Specifications (TAP Connection)
47
BCLK to Core Logic Offset
48
BCLK*, PICCLK, and TCK Generic Clock Waveform
49
System Bus Valid Delay Timings
49
System Bus Setup and Hold Timings
49
System Bus Reset and Configuration Timings (for the S.E.P. and PPGA Packages)
50
System Bus Reset and Configuration Timings (for the FC-PGA/FC-PGA2 Package)
50
Power-On Reset and Configuration Timings
51
Test Timings (TAP Connection)
51
Test Reset Timings
51
System Bus Signal Simulations
52
System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines
52
BCLK Signal Quality Specifications for Simulation at the Processor Core (for both S.E.P. and PPGA Packages)
52
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins
53
BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins (for the FC-PGA/FC-PGA2 Packages)
53
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers
54
BCLK Signal Quality Guidelines for Edge Finger Measurement (for the S.E
54
AGTL+ Signal Quality Specifications and Measurement Guidelines
55
AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core (for both the S.E.P. and PPGA Packages)
55
AGTL+ Signal Groups Ringback Tolerance Specifications at the
55
Processor Pins (for FC-PGA/FC-PGA2 Packages)
55
Low to High AGTL+ Receiver Ringback Tolerance
56
AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger Measurement on the S.E
56
Non-AGTL+ Signal Quality Specifications and Measurement Guidelines
57
Overshoot/Undershoot Guidelines
57
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback
57
Ringback Specification
58
Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Core (S.E.P. and PPGA Packages)
58
Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement (S.E
58
Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Pins (FC-PGA/FC-PGA2 Packages)
58
Settling Limit Guideline
59
AGTL+ Signal Quality Specifications and Measurement Guidelines (FC-PGA/FC-PGA2 Packages)
59
Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages)
59
Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages)
59
Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2 Packages)
60
Activity Factor (FC-PGA/FC-PGA2 Packages)
60
Reading Overshoot/Undershoot Specification Tables (FC-PGA/FC-PGA2 Packages)
61
Example Platform Information
61
Determining if a System Meets the Overshoot/Undershoot Specifications (FC-PGA/FC-PGA2 Packages)
62
Mhz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PGA2 Packages)
62
Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform (FC-PGA/FC-PGA2 Packages)
63
Mhz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PGA2 Packages)
63
Non-AGTL+ Signal Quality Specifications and Measurement Guidelines
64
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback
64
Thermal Specifications and Design Considerations
65
Thermal Specifications
65
Processor Power for the PPGA and FC-PGA Packages
66
Processor Functional die Layout (CPUID 0686H)
67
Processor Functional die Layout (up to CPUID 0683H)
67
Thermal Diode
68
Thermal Diode Parameters (S.E.P. and PPGA Packages)
68
Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages)
68
Thermal Diode Interface
68
Mechanical Specifications
69
Package
69
Materials Information
69
Signal Listing (S.E
70
Processor Substrate Dimensions (S.E
70
Processor Substrate Primary/Secondary Side Dimensions (S.E
70
S.E.P. Package Signal Listing by Pin Number
71
S.E.P. Package Signal Listing by Signal Name
75
PPGA Package
79
PPGA Package Materials Information
79
Package Dimensions (PPGA Package)
79
Package Dimensions (PPGA Package)
80
Information Summary (PPGA Package)
80
PPGA Package Signal Listing
81
PPGA Package (Pin Side View)
81
PPGA Package Signal Listing by Pin Number
86
PPGA Package Signal Listing in Order by Signal Name
88
FC-PGA/FC-PGA2 Packages
92
FC-PGA/FC-PGA2 Packages)
92
FC-PGA Mechanical Specifications
92
Package Dimensions (FC-PGA Package)
92
Package Dimensions (FC-PGA Package)
93
Processor die Loading Parameters (FC-PGA Package)
93
Mechanical Specifications (FC-PGA2 Package)
94
Package Dimensions (FC-PGA2 Package)
94
Package Dimensions (FC-PGA2 Package)
95
Processor Case Loading Parameters (FC-PGA2 Package)
95
Recommended Mechanical Keep-Out Zones (FC-PGA2 Package)
96
Volumetric Keep-Out
96
Component Keep-Out
96
FC-PGA/FC-PGA2 Package Signal List
97
Package Dimensions (FC-PGA/FC-PGA2 Packages)
97
FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name
98
FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number
107
Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages)
108
Top Side Processor Markings (PPGA Package)
108
Top Side Processor Markings (FC-PGA Package)
108
Top Side Processor Markings (FC-PGA2 Package)
108
Heatsink Volumetric Keepout Zone Guidelines
109
Boxed Processor Specifications
110
Mechanical Specifications for the Boxed Intel
110
Celeron ® Processor
110
Mechanical Specifications for the S.E
110
Side View Space Requirements for the Boxed Processor in the S.E
111
Boxed Processor Heatsink Weight
112
Boxed Processor Retention Mechanism
112
Front View Space Requirements for the Boxed Processor in the S.E
112
Boxed Processor Fan Heatsink Spatial Dimensions for the S.E
112
Mechanical Specifications for the PPGA Package
113
Side View Space Requirements for the Boxed Processor in the PPGA Package
113
Boxed Processor Heatsink Weight
114
Mechanical Specifications for the FC-PGA/FC-PGA2 Packages
114
Conceptual Drawing of the Boxed Intel
114
Dimensions of Mechanical Step Feature in Heatsink Base for the
114
FC-PGA/FC-PGA2 Packages
114
Boxed Processor Heatsink Weight
115
Thermal Specifications
115
Thermal Requirements for the Boxed Intel
115
Celeron ® Processor
115
Boxed Processor Cooling Requirements
115
Top View Airspace Requirements for the Boxed Processor in the S.E
115
Side View Airspace Requirements for the Boxed Intel
116
Volumetric Keepout Requirements for the Boxed Fan Heatsink
116
Boxed Processor Thermal Cooling Solution Clip
117
Electrical Requirements for the Boxed Intel
117
Electrical Requirements
117
Clip Keepout Requirements for the 370-Pin (Top View)
117
Boxed Processor Fan Heatsink Power Cable Connector Description
118
Fan Heatsink Power and Signal Specifications
118
Motherboard Power Header Placement for the S.E
119
Motherboard Power Header Placement Relative to the 370-Pin Socket
119
Alphabetical Signal Reference
120
Signal Summaries
126
Processor Signal Description
120
Output Signals
126
Input Signals
127
Input/Output Signals (Single Driver)
128
Input/Output Signals (Multiple Driver)
128
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Intel CELERON 1.10 GHZ Specifications
General
Brand
Intel
Model
CELERON 1.10 GHZ
Category
Computer Hardware
Language
English
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