54 Datasheet
Intel
®
Celeron
®
Processor up to 1.10 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot measurement guideline.
3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal may dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This
guideline is an absolute value.
4. The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The
midpoint voltage level of this ledge should be within the range of the guideline.
5. The ledge (V7) is allowed to have peak-to-peak oscillation as given in the guideline.
Table 30. BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package)
T# Parameter Min Nom Max Unit Figure Notes
V1’: BCLK V
IL
0.5 V 12
V2’: BCLK V
IH
2.0 V 12
V3’: V
IN Absolute Voltage Range –0.5 3.3 V 12 2
V4’: Rising Edge Ringback 2.0 V 12 3
V5’: Falling Edge Ringback 0.5 V 12 3
V6’: T
line Ledge Voltage 1.0 1.7 V 12 At Ledge Midpoint
4
V7’: Tline Ledge Oscillation 0.2 V 12 Peak-to-Peak
5
Figure 12. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers
T3
V3
V5
V3
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