Intel CELERON 1.10 GHZ User Manual

Datasheet 5
Intel
®
Celeron
®
Processor up to 1.10 GHz
Figures
1 Clock Control State Machine...............................................................................16
2 BCLK to Core Logic Offset..................................................................................48
3 BCLK*, PICCLK, and TCK Generic Clock Waveform .........................................49
4 System Bus Valid Delay Timings ........................................................................49
5 System Bus Setup and Hold Timings..................................................................49
6 System Bus Reset and Configuration Timings (For the S.E.P. and
PPGA Packages) ................................................................................................50
7 System Bus Reset and Configuration Timings (For the
FC-PGA/FC-PGA2 Package)..............................................................................50
8 Power-On Reset and Configuration Timings.......................................................51
9 Test Timings (TAP Connection) ..........................................................................51
10 Test Reset Timings .............................................................................................51
11 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins .....53
12 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor
Edge Fingers.......................................................................................................54
13 Low to High AGTL+ Receiver Ringback Tolerance.............................................56
14 Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback .....................57
15 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
(FC-PGA/FC-PGA2 Packages)...........................................................................63
16 Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback ....................64
17 Processor Functional Die Layout (CPUID 0686h)...............................................67
18 Processor Functional Die Layout (up to CPUID 0683h)......................................67
19 Processor Substrate Dimensions (S.E.P. Package) ...........................................70
20 Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)....70
21 Package Dimensions (PPGA Package) ..............................................................79
22 PPGA Package (Pin Side View)..........................................................................81
23 Package Dimensions (FC-PGA Package)...........................................................92
24 Package Dimensions (FC-PGA2 Package).........................................................94
25 Volumetric Keep-Out...........................................................................................96
26 Component Keep-Out .........................................................................................96
27 Package Dimensions (FC-PGA/FC-PGA2 Packages) ........................................97
28 Top Side Processor Markings (PPGA Package)...............................................108
29 Top Side Processor Markings (FC-PGA Package) ...........................................108
30 Top Side Processor Markings (FC-PGA2 Package) .........................................108
31 Retention Mechanism for the Boxed Intel® Celeron
®
Processor in the
S.E.P. Package .................................................................................................111
32 Side View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................111
33 Front View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................112
34 Boxed Intel
®
Celeron
®
Processor in the PPGA Package..................................113
35 Side View Space Requirements for the Boxed Processor in the PPGA
Package ............................................................................................................113
36 Conceptual Drawing of the Boxed Intel
®
Celeron
®
Processor in the
370-Pin Socket (FC-PGA/FC-PGA2 Packages)................................................114
37 Dimensions of Mechanical Step Feature in Heatsink Base for the
FC-PGA/FC-PGA2 Packages ...........................................................................114
38 Top View Airspace Requirements for the Boxed Processor in the
S.E.P. Package .................................................................................................115

Intel CELERON 1.10 GHZ Specifications

General

Brand	Intel
Model	CELERON 1.10 GHZ
Category	Computer Hardware
Language	English